Searched refs:CXL (Results 1 - 25 of 28) sorted by relevance

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/linux-master/tools/testing/cxl/
H A Dcxl_core_exports.c7 EXPORT_SYMBOL_NS_GPL(cxl_num_decoders_committed, CXL);
/linux-master/drivers/cxl/core/
H A Dsuspend.c18 EXPORT_SYMBOL_NS_GPL(cxl_mem_active_inc, CXL);
24 EXPORT_SYMBOL_NS_GPL(cxl_mem_active_dec, CXL);
H A Dpmem.c13 * The core CXL PMEM infrastructure supports persistent memory
14 * provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL
15 * 'bridge' device is added at the root of a CXL device topology if
17 * CXL window. That root-level bridge corresponds to a LIBNVDIMM 'bus'
18 * device. Then for each cxl_memdev in the CXL device topology a bridge
20 * are registered native LIBNVDIMM uapis are translated to CXL
52 EXPORT_SYMBOL_NS_GPL(to_cxl_nvdimm_bridge, CXL);
58 EXPORT_SYMBOL_NS_GPL(is_cxl_nvdimm_bridge, CXL);
81 EXPORT_SYMBOL_NS_GPL(cxl_find_nvdimm_bridge, CXL);
126 * @port: CXL por
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H A Dregs.c16 * CXL device capabilities are enumerated by PCI DVSEC (Designated
19 * mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and
28 * cxl_probe_component_regs() - Detect CXL Component register blocks
33 * See CXL 2.0 8.2.4 Component Register Layout and Definition
34 * See CXL 2.0 8.2.5.5 CXL Device Register Interface
47 * CXL.cache and CXL.mem registers are at offset 0x1000 as defined in
48 * CXL 2.0 8.2.4 Table 141.
56 "Couldn't locate the CXL
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H A Dport.c22 * The CXL core provides a set of interfaces that can be consumed by CXL aware
24 * regions, memory devices, ports, and decoders. CXL aware drivers must register
25 * with the CXL core via these interfaces in order to be able to participate in
26 * cross-device interleave coordination. The CXL core also establishes and
29 * CXL core introduces sysfs hierarchy to control the devices that are
440 EXPORT_SYMBOL_NS_GPL(to_cxl_root_decoder, CXL);
474 EXPORT_SYMBOL_NS_GPL(is_endpoint_decoder, CXL);
480 EXPORT_SYMBOL_NS_GPL(is_root_decoder, CXL);
486 EXPORT_SYMBOL_NS_GPL(is_switch_decoder, CXL);
2347 MODULE_IMPORT_NS(CXL); variable
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H A Dpmu.c68 EXPORT_SYMBOL_NS_GPL(devm_cxl_pmu_add, CXL);
H A Dmemdev.c199 /* CXL 3.0 Spec 8.2.9.8.4.1 Separate pmem and ram poison requests */
252 EXPORT_SYMBOL_NS_GPL(cxl_trigger_poison_list, CXL);
375 EXPORT_SYMBOL_NS_GPL(cxl_inject_poison, CXL);
404 * In CXL 3.0 Spec 8.2.9.8.4.3, the Clear Poison mailbox command
439 EXPORT_SYMBOL_NS_GPL(cxl_clear_poison, CXL);
583 EXPORT_SYMBOL_NS_GPL(cxl_memdev_update_perf, CXL);
596 EXPORT_SYMBOL_NS_GPL(is_cxl_memdev, CXL);
615 EXPORT_SYMBOL_NS_GPL(set_exclusive_cxl_commands, CXL);
630 EXPORT_SYMBOL_NS_GPL(clear_exclusive_cxl_commands, CXL);
757 * See CXL
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H A Dmbox.c20 * Core implementation of the CXL 2.0 Type-3 Memory Device Mailbox. The
281 EXPORT_SYMBOL_NS_GPL(cxl_internal_send_cmd, CXL);
773 /* See CXL 2.0 Table 170. Get Log Input Payload */
785 * CXL devices have optional support for certain commands. This function will
838 EXPORT_SYMBOL_NS_GPL(cxl_enumerate_cmds, CXL);
854 EXPORT_SYMBOL_NS_GPL(cxl_event_trace_record, CXL);
1005 * See CXL rev 3.0 @8.2.9.2.2 Get Event Records
1006 * See CXL rev 3.0 @8.2.9.2.3 Clear Event Records
1021 EXPORT_SYMBOL_NS_GPL(cxl_mem_get_event_records, CXL);
1033 * See CXL
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H A Dpci.c19 * Compute Express Link protocols are layered on top of PCIe. CXL core provides
20 * a set of helpers for CXL interactions which occur via PCIe.
104 EXPORT_SYMBOL_NS_GPL(devm_cxl_port_enumerate_dports, CXL);
212 EXPORT_SYMBOL_NS_GPL(cxl_await_media_ready, CXL);
220 * Memory_Info_Valid: When set, indicates that the CXL Range 1 Size high
222 * deassertion of reset to CXL device. Likely it is already set by the
352 * HDM decoders (values > 2 are also undefined as of CXL 2.0). As this
353 * driver is for a spec defined class code which must be CXL.mem
354 * capable, there is no point in continuing to enable CXL.mem.
426 EXPORT_SYMBOL_NS_GPL(cxl_dvsec_rr_decode, CXL);
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H A Dhdm.c14 * CXL 2.0 specification, is managed by an array of HDM Decoder register
15 * instances per CXL port and per CXL endpoint. Define common helpers
43 * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
47 * CXL region is enumerated / activated.
68 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_passthrough_decoder, CXL);
189 EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_hdm, CXL);
211 EXPORT_SYMBOL_NS_GPL(cxl_dpa_debug, CXL);
348 EXPORT_SYMBOL_NS_GPL(devm_cxl_dpa_reserve, CXL);
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H A Dcdat.c418 EXPORT_SYMBOL_NS_GPL(cxl_endpoint_parse_cdat, CXL);
515 EXPORT_SYMBOL_NS_GPL(cxl_switch_parse_cdat, CXL);
547 MODULE_IMPORT_NS(CXL); variable
H A Dregion.c19 * CXL Regions represent mapped memory capacity in system physical address
20 * space. Whereas the CXL Root Decoders identify the bounds of potential CXL
872 * Per CXL Spec 3.1 8.2.4.20.12 software must commit decoders
1029 * The attach event is an opportunity to validate CXL decode setup
1500 dev_err(&cxlr->dev, "mismatched CXL topologies detected\n");
2213 EXPORT_SYMBOL_NS_GPL(is_cxl_region, CXL);
2551 EXPORT_SYMBOL_NS_GPL(is_cxl_pmem_region, CXL);
2560 EXPORT_SYMBOL_NS_GPL(to_cxl_pmem_region, CXL);
2629 * CXL 3.
3204 MODULE_IMPORT_NS(CXL); variable
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/linux-master/drivers/acpi/apei/
H A Deinj-cxl.c3 * CXL Error INJection support. Used by CXL core to inject
4 * protocol errors into CXL ports.
20 { ACPI_EINJ_CXL_CACHE_CORRECTABLE, "CXL.cache Protocol Correctable" },
21 { ACPI_EINJ_CXL_CACHE_UNCORRECTABLE, "CXL.cache Protocol Uncorrectable non-fatal" },
22 { ACPI_EINJ_CXL_CACHE_FATAL, "CXL.cache Protocol Uncorrectable fatal" },
23 { ACPI_EINJ_CXL_MEM_CORRECTABLE, "CXL.mem Protocol Correctable" },
24 { ACPI_EINJ_CXL_MEM_UNCORRECTABLE, "CXL.mem Protocol Uncorrectable non-fatal" },
25 { ACPI_EINJ_CXL_MEM_FATAL, "CXL.mem Protocol Uncorrectable fatal" },
48 EXPORT_SYMBOL_NS_GPL(einj_cxl_available_error_type_show, CXL);
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/linux-master/tools/testing/cxl/test/
H A Dmock.c150 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_setup_hdm, CXL);
165 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_passthrough_decoder, CXL);
182 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_enumerate_decoders, CXL);
197 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_port_enumerate_dports, CXL);
212 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_await_media_ready, CXL);
229 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL);
245 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dvsec_rr_decode, CXL);
269 EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, CXL);
286 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_rcd_component_reg_phys, CXL);
300 EXPORT_SYMBOL_NS_GPL(__wrap_cxl_endpoint_parse_cdat, CXL);
304 MODULE_IMPORT_NS(CXL); variable
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/linux-master/drivers/dax/
H A Dcxl.c48 MODULE_IMPORT_NS(CXL); variable
/linux-master/include/linux/
H A Dfw_table.h52 /* CXL is the only non-ACPI consumer of the FIRMWARE_TABLE library */
57 #define EXPORT_SYMBOL_FWTBL_LIB(x) EXPORT_SYMBOL_NS_GPL(x, CXL)
/linux-master/drivers/cxl/
H A Dport.c16 * port. All descendant ports of a CXL root port (described by platform
24 * status) the connectivity of the CXL.mem protocol throughout the
130 * This can't fail in practice as CXL root exit unregisters all
213 MODULE_IMPORT_NS(CXL); variable
H A Dmem.c14 * CXL memory endpoint devices and switches are CXL capable devices that are
15 * participating in CXL.mem protocol. Their functionality builds on top of the
16 * CXL.io protocol that allows enumerating and configuring components via
19 * The cxl_mem driver owns kicking off the enumeration of this CXL.mem
20 * capability. With the detection of a CXL capable endpoint, the driver will
24 * cxl_mem driver adds the device it is bound to as a CXL endpoint-port for use
151 dev_err(dev, "CXL port topology not found\n");
164 dev_err(dev, "CXL port topology %s not enabled\n",
186 * The kernel may be operating out of CXL memor
256 MODULE_IMPORT_NS(CXL); variable
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H A Dpmem.c268 .provider_name = "CXL",
392 * TODO enable CXL labels which skip the need for 'interleave-set cookie'
461 MODULE_IMPORT_NS(CXL); variable
H A Dpci.c22 * This implements the PCI exclusive functionality for a CXL device as it is
23 * defined by the Compute Express Link specification. CXL devices may surface
24 * certain functionality even if it isn't CXL enabled. While this driver is
25 * focused around the PCI specific aspects of a CXL device, it binds to the
26 * specific CXL memory device class code, and therefore the implementation of
27 * cxl_pci is focused around CXL memory devices.
30 * - Create the memX device and register on the CXL bus.
33 * - Registers a CXL mailbox with cxl_core.
40 /* CXL 2.0 - 8.2.8.4 */
44 * CXL 2.
979 MODULE_IMPORT_NS(CXL); variable
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H A Dacpi.c27 * CXL Specification 3.0 Table 9-22
98 /* Does this CXIMS entry apply to the given CXL Window? */
355 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", ctx->id++);
571 * VH mode it will be bound to the CXL host bridge's port
623 dev_info(bridge, "host supports CXL (restricted)\n");
633 "CXL CHBS version mismatch, skip port registration\n");
650 dev_info(bridge, "host supports CXL\n");
722 * add_cxl_resources() - reflect CXL fixed memory windows in iomem_resource
723 * @cxl_res: A standalone resource tree where each CXL window is a sibling
725 * Walk each CXL windo
916 MODULE_IMPORT_NS(CXL); variable
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/linux-master/drivers/pci/pcie/
H A Daer.c233 EXPORT_SYMBOL_NS_GPL(pcie_aer_is_native, CXL);
804 EXPORT_SYMBOL_NS_GPL(pci_print_aer, CXL);
972 * Function 0 DVSEC control the CXL functionality of the
973 * entire device (CXL 3.0, 8.1.3).
979 * CXL Memory Devices must have the 502h class code set (CXL
1036 * RCH's downstream port. Check and handle them in the CXL.mem
1072 pci_info(rcec, "CXL: Internal errors unmasked");
/linux-master/kernel/
H A Dresource.c952 * resource discovery, and late discovery of CXL resources are expected
954 * CXL, is a module.
956 EXPORT_SYMBOL_NS_GPL(insert_resource_expand_to_fit, CXL);
2000 * Buses like CXL, that can dynamically instantiate new memory regions,
2015 EXPORT_SYMBOL_NS_GPL(alloc_free_mem_region, CXL);
/linux-master/drivers/perf/
H A Dcxl_pmu.c6 * The CXL 3.0 specification includes a standard Performance Monitoring Unit,
7 * called the CXL PMU, or CPMU. In order to allow a high degree of
11 * Details in CXL rev 3.0 section 8.2.7 CPMU Register Interface
66 /* CXL rev 3.0 Table 13-5 Events under CXL Vendor ID */
346 /* For CXL spec defined events */
352 /* CXL rev 3.0 Table 3-17 - Device to Host Requests */
368 /* CXL rev 3.0 Table 3-20 - D2H Repsonse Encodings */
376 /* CXL rev 3.0 Table 3-21 - CXL
987 MODULE_IMPORT_NS(CXL); variable
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/linux-master/drivers/acpi/numa/
H A Dhmat.c135 * Only supports device handles that are ACPI. Assume ACPI0016 HID for CXL.
154 EXPORT_SYMBOL_NS_GPL(acpi_get_genport_coordinates, CXL);

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