cxl/core/regs.c

16  * CXL device capabilities are enumerated by PCI DVSEC (Designated
19  * mandated by CXL Section 8.1.12.2 Memory Device PCIe Capabilities and
28  * cxl_probe_component_regs() - Detect CXL Component register blocks
33  * See CXL 2.0 8.2.4 Component Register Layout and Definition
34  * See CXL 2.0 8.2.5.5 CXL Device Register Interface
47 	 * CXL.cache and CXL.mem registers are at offset 0x1000 as defined in
48 	 * CXL 2.0 8.2.4 Table 141.
56 			"Couldn't locate the CXL.cache and CXL.mem capability array header.\n");
109 EXPORT_SYMBOL_NS_GPL(cxl_probe_component_regs, CXL);
112  * cxl_probe_device_regs() - Detect CXL Device register blocks
114  * @base: Mapping of CXL 2.0 8.2.8 CXL Device Register Interface
177 EXPORT_SYMBOL_NS_GPL(cxl_probe_device_regs, CXL);
235 EXPORT_SYMBOL_NS_GPL(cxl_map_component_regs, CXL);
269 EXPORT_SYMBOL_NS_GPL(cxl_map_device_regs, CXL);
294  * @pdev: The CXL PCI device to enumerate.
302  * A CXL DVSEC may point to one or more register blocks, search for them
347 EXPORT_SYMBOL_NS_GPL(cxl_find_regblock_instance, CXL);
351  * @pdev: The CXL PCI device to enumerate.
357  * A CXL DVSEC may point to one or more register blocks, search for them
365 EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL);
369  * @pdev: The CXL PCI device to enumerate.
388 EXPORT_SYMBOL_NS_GPL(cxl_count_regblock, CXL);
402 EXPORT_SYMBOL_NS_GPL(cxl_map_pmu_regs, CXL);
414 	dev_dbg(host, "Mapped CXL Memory Device resource %pa\n", &map->resource);
471 EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, CXL);
523 	 * RCRB's BAR[0..1] point to component block containing CXL
528 	if (!request_mem_region(rcrb, SZ_4K, "CXL RCRB"))
545 	 * Sanity check, see CXL 3.0 Figure 9-8 CXL Device that Does Not
580 EXPORT_SYMBOL_NS_GPL(cxl_rcd_component_reg_phys, CXL);