Lines Matching refs:CXL
14 * CXL 2.0 specification, is managed by an array of HDM Decoder register
15 * instances per CXL port and per CXL endpoint. Define common helpers
43 * Per the CXL specification (8.2.5.12 CXL HDM Decoder Capability Structure)
47 * CXL region is enumerated / activated.
68 EXPORT_SYMBOL_NS_GPL(devm_cxl_add_passthrough_decoder, CXL);
189 EXPORT_SYMBOL_NS_GPL(devm_cxl_setup_hdm, CXL);
211 EXPORT_SYMBOL_NS_GPL(cxl_dpa_debug, CXL);
348 EXPORT_SYMBOL_NS_GPL(devm_cxl_dpa_reserve, CXL);
589 * Per CXL 2.0 8.2.5.12.20 Committing Decoder Programming, hardware must set
635 * For endpoint decoders hosted on CXL memory devices that
951 * timeout has elapsed. The commit timeout is 10ms (CXL 2.0
1029 EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_decoders, CXL);