| /linux-master/drivers/clk/ralink/ |
| H A D | clk-mtmips.c | 665 #define CLK_BASE(_name, _parent, _recalc) { \ macro
680 { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
684 { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
688 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
689 { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
693 { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
694 { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
698 { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
699 { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
700 { CLK_BASE("bu
[all...] |
| H A D | clk-mt7621.c | 295 #define CLK_BASE(_name, _parent, _recalc) { \ macro
310 { CLK_BASE("xtal", NULL, mt7621_xtal_recalc_rate) },
311 { CLK_BASE("cpu", "xtal", mt7621_cpu_recalc_rate) },
312 { CLK_BASE("bus", "cpu", mt7621_bus_recalc_rate) },
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| /linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr_internal.h | 81 #define CLK_BASE(inst) \ macro
85 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vega10_reg_init.c | 53 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
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| H A D | vega20_reg_init.c | 51 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
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| /linux-master/drivers/gpu/drm/amd/include/ |
| H A D | cyan_skillfish_ip_offset.h | 43 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | navi10_ip_offset.h | 43 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x00017E00, 0x0001B000 } }, variable in typeref:struct:IP_BASE
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| H A D | vega20_ip_offset.h | 43 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } }, variable in typeref:struct:IP_BASE
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| H A D | yellow_carp_offset.h | 33 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | renoir_ip_offset.h | 51 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017E00, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | vega10_ip_offset.h | 201 static const struct IP_BASE __maybe_unused CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } }, variable in typeref:struct:__maybe_unused
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| H A D | sienna_cichlid_ip_offset.h | 44 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | beige_goby_ip_offset.h | 45 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | navi12_ip_offset.h | 44 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | navi14_ip_offset.h | 44 static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x02401800, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | dimgrey_cavefish_ip_offset.h | 44 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | aldebaran_ip_offset.h | 42 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | vangogh_ip_offset.h | 56 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | arct_ip_offset.h | 45 static const struct IP_BASE CLK_BASE ={ { { { 0x000120C0, 0x00016C00, 0x00401800, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_clk_mgr.c | 72 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0, 0, 0 } }, variable in typeref:struct:IP_BASE
105 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn314/ |
| H A D | dcn314_resource.c | 210 #define CLK_BASE(seg) \ macro
214 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 186 #define CLK_BASE(seg) \ macro
190 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.c | 70 (CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 59 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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| /linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 51 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
|