Searched refs:base (Results 1 - 25 of 1019) sorted by relevance

1234567891011>>

/u-boot/arch/mips/mach-pic32/
H A Dreset.c19 void __iomem *base; local
21 base = pic32_get_syscfg_base();
24 writel(LOCK_KEY, base + SYSKEY);
25 writel(UNLOCK_KEY1, base + SYSKEY);
26 writel(UNLOCK_KEY2, base + SYSKEY);
29 writel(0x1, base + RSWRST);
30 (void) readl(base + RSWRST);
/u-boot/board/intel/galileo/
H A Dgalileo.c23 u32 base, port, val; local
25 /* retrieve the GPIO IO base */
26 qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
27 base = (base & 0xffff) & ~0x7f;
30 port = base + 0x20;
36 port = base + 0x24;
42 port = base + 0x28;
50 u32 base, port, val; local
52 /* retrieve the GPIO IO base */
[all...]
/u-boot/arch/arm/include/asm/mach-imx/
H A Dmu_hal.h9 void mu_hal_init(ulong base);
10 int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg);
11 int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg);
/u-boot/arch/mips/mach-mtmips/mt7628/
H A Dserial.c14 void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); local
17 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M);
19 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M);
21 setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M);
23 setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M);
24 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M,
27 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M);
28 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M,
/u-boot/drivers/spi/
H A Dtegra_spi.h9 ulong base; member in struct:tegra_spi_plat
/u-boot/include/dm/platform_data/
H A Dserial_bcm283x_mu.h15 * @base: Register base address
18 unsigned long base; member in struct:bcm283x_mu_serial_plat
H A Dserial_coldfire.h12 * @base: Uart port base register address
17 unsigned long base; member in struct:coldfire_serial_plat
/u-boot/arch/mips/mach-mtmips/mt7621/
H A Dserial.c14 void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); local
17 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART1_MODE);
19 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART2_MODE_M);
21 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART3_MODE_M);
/u-boot/arch/mips/mach-mtmips/mt7621/spl/
H A Dserial.c14 void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); local
17 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART1_MODE);
19 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART2_MODE_M);
21 clrbits_32(base + SYSCTL_GPIOMODE_REG, UART3_MODE_M);
/u-boot/drivers/clk/imx/
H A Dclk-imx8mp.c194 void __iomem *base; local
197 base = (void *)ANATOP_BASE_ADDR;
199 clk_dm(IMX8MP_DRAM_PLL_REF_SEL, imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
200 clk_dm(IMX8MP_ARM_PLL_REF_SEL, imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
201 clk_dm(IMX8MP_SYS_PLL1_REF_SEL, imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
202 clk_dm(IMX8MP_SYS_PLL2_REF_SEL, imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
203 clk_dm(IMX8MP_SYS_PLL3_REF_SEL, imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
205 clk_dm(IMX8MP_DRAM_PLL, imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel", base + 0x50,
207 clk_dm(IMX8MP_ARM_PLL, imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", base + 0x84,
209 clk_dm(IMX8MP_SYS_PLL1, imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel", base
[all...]
H A Dclk-imx8mn.c123 void __iomem *base; local
125 base = (void *)ANATOP_BASE_ADDR;
128 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
131 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
134 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
137 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
140 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
145 base + 0x50, &imx_1443x_dram_pll));
148 base + 0x84, &imx_1416x_pll));
151 base
[all...]
H A Dclk-imx8mq.c148 void __iomem *base; local
150 base = (void *)ANATOP_BASE_ADDR;
156 imx_clk_mux("dram_pll_ref_sel", base + 0x60, 0, 2,
159 imx_clk_mux("arm_pll_ref_sel", base + 0x28, 0, 2,
162 imx_clk_mux("gpu_pll_ref_sel", base + 0x18, 0, 2,
165 imx_clk_mux("vpu_pll_ref_sel", base + 0x20, 0, 2,
168 imx_clk_mux("sys3_pll_ref_sel", base + 0x48, 0, 2,
171 imx_clk_mux("audio_pll1_ref_sel", base + 0x0, 0, 2,
174 imx_clk_mux("audio_pll2_ref_sel", base + 0x8, 0, 2,
177 imx_clk_mux("video_pll1_ref_sel", base
[all...]
H A Dclk-imx6q.c42 void *base; local
45 base = (void *)ANATOP_BASE_ADDR;
49 base + 0x30, 0x1));
52 base + 0x10, 0x3));
56 imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0));
58 imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2));
60 imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3));
62 imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
65 base = dev_read_addr_ptr(dev);
66 if (!base)
[all...]
H A Dclk-imx8mm.c124 void __iomem *base;
126 base = (void *)ANATOP_BASE_ADDR;
129 imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
132 imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
135 imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
138 imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
141 imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
146 base + 0x50, &imx_1443x_dram_pll));
149 base + 0x84, &imx_1416x_pll));
152 base
113 void __iomem *base; local
[all...]
/u-boot/arch/arm/mach-sunxi/
H A Ddram_helpers.c29 * Test if memory at offset matches memory at a certain base
34 bool mctl_mem_matches_base(u32 offset, ulong base) argument
41 val_base = readl(base);
42 val_offset = readl(base + offset);
45 writel(0, base);
46 writel(0xaa55aa55, base + offset);
49 ret = readl(base) == readl(base + offset);
52 writel(val_base, base);
53 writel(val_offset, base
[all...]
/u-boot/drivers/pch/
H A Dpch9.c29 u32 base; local
37 * GPIO base address register bit0 is reserved (read returns 0),
41 dm_pci_read_config32(dev, GPIO_BASE, &base);
42 if (base == 0x00000000 || base == 0xffffffff) {
53 *gbasep = base & 1 ? base & ~3 : base & ~15;
60 u32 base; local
62 dm_pci_read_config32(dev, IO_BASE, &base);
[all...]
/u-boot/arch/mips/mach-mtmips/mt7620/
H A Dserial.c14 void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); local
17 clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M,
20 clrbits_32(base + SYSCTL_GPIOMODE_REG, UARTL_GPIO_MODE);
27 void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); local
30 clrbits_32(base + SYSCTL_GPIOMODE_REG, UARTL_GPIO_MODE);
32 clrsetbits_32(base + SYSCTL_GPIOMODE_REG, UARTF_SHARE_MODE_M,
/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-base-ld20.c35 void __iomem *base = sc_base + reg_base; local
39 tmp = readl(base); /* SSCPLLCTRL */
44 writel(tmp, base);
46 tmp = readl(base + 4);
51 writel(tmp, base + 4);
56 tmp = readl(base + 4); /* SSCPLLCTRL2 */
58 writel(tmp, base + 4);
65 void __iomem *base = sc_base + reg_base; local
68 tmp = readl(base); /* SSCPLLCTRL */
70 writel(tmp, base);
77 void __iomem *base = sc_base + reg_base; local
90 void __iomem *base = sc_base + reg_base; local
110 void __iomem *base = sc_base + reg_base; local
[all...]
/u-boot/arch/arm/include/asm/arch-hi6220/
H A Dgpio.h17 u8 *base; /* address of registers in physical memory */ member in struct:gpio_bank
23 ulong base; /* address of registers in physical memory */ member in struct:hikey_gpio_plat
/u-boot/arch/arm/include/asm/
H A Domap_gpio.h30 ulong base; /* address of registers in physical memory */ member in struct:omap_gpio_plat
37 void *base; member in struct:gpio_bank
/u-boot/drivers/bios_emulator/
H A Dbiosemui.h67 #define readb_le(base) *((u8*)(base))
68 #define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8))
69 #define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \
70 ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base)
[all...]
/u-boot/include/dm/
H A Dsimple_bus.h10 fdt_addr_t base; member in struct:simple_bus_plat
/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-usb-otg.c12 int clk_usb_otg_enable(void *base) argument
16 switch ((u32) base) {
21 printf("%s: base 0x%p not found\n", __func__, base);
/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-usb-otg.c12 int clk_usb_otg_enable(void *base) argument
16 switch ((u32) base) {
21 printf("%s: base 0x%p not found\n", __func__, base);
/u-boot/drivers/clk/microchip/
H A Dmpfs_clk.h13 * @base: base address of the mpfs system register.
17 int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
21 * @base: base address of the mpfs system register.
25 int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent);
29 * @base: base address of the mpfs system register.
33 int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev);

Completed in 271 milliseconds

1234567891011>>