1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8#include <asm/io.h> 9#include "mt7628.h" 10 11void mtmips_spl_serial_init(void) 12{ 13#ifdef CONFIG_SPL_SERIAL 14 void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); 15 16#if CONFIG_CONS_INDEX == 1 17 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M); 18#elif CONFIG_CONS_INDEX == 2 19 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M); 20#elif CONFIG_CONS_INDEX == 3 21 setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M); 22#ifdef CONFIG_SPL_UART2_SPIS_PINMUX 23 setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M); 24 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M, 25 1 << UART2_MODE_S); 26#else 27 clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M); 28 clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M, 29 1 << SPIS_MODE_S); 30#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */ 31#endif /* CONFIG_CONS_INDEX */ 32#endif /* CONFIG_SPL_SERIAL */ 33} 34