clk/imx/clk-imx8mn.c

123 	void __iomem *base;
125 	base = (void *)ANATOP_BASE_ADDR;
128 	       imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
131 	       imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
134 	       imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
137 	       imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
140 	       imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
145 			       base + 0x50, &imx_1443x_dram_pll));
148 			       base + 0x84, &imx_1416x_pll));
151 			       base + 0x94, &imx_1416x_pll));
154 			       base + 0x104, &imx_1416x_pll));
157 			       base + 0x114, &imx_1416x_pll));
161 	       imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
166 	       imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
171 	       imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
176 	       imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
181 	       imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
189 			    base + 0x50, 13));
192 			    base + 0x84, 11));
195 			    base + 0x94, 11));
198 			    base + 0x104, 11));
201 			    base + 0x114, 11));
242 	base = dev_read_addr_ptr(dev);
243 	if (!base)
247 	       imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
250 	       imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
253 				base + 0x8000, 0, 3));
257 					    base + 0x9000));
259 	       imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
263 				   base + 0x8880));
267 					    base + 0x8900));
269 		imx8m_clk_composite("usb_bus", imx8mn_usb_bus_sels, base + 0x8b80));
274 				   base + 0xac00));
277 				   base + 0xac80));
279 	       imx8m_clk_composite("i2c1", imx8mn_i2c1_sels, base + 0xad00));
281 	       imx8m_clk_composite("i2c2", imx8mn_i2c2_sels, base + 0xad80));
283 	       imx8m_clk_composite("i2c3", imx8mn_i2c3_sels, base + 0xae00));
285 	       imx8m_clk_composite("i2c4", imx8mn_i2c4_sels, base + 0xae80));
287 	       imx8m_clk_composite("wdog", imx8mn_wdog_sels, base + 0xb900));
290 				   base + 0xbc80));
292 	       imx8m_clk_composite("nand", imx8mn_nand_sels, base + 0xab00));
294 	       imx8m_clk_composite("qspi", imx8mn_qspi_sels, base + 0xab80));
296 		imx8m_clk_composite("usb_core_ref", imx8mn_usb_core_sels, base + 0xb100));
298 		imx8m_clk_composite("usb_phy_ref", imx8mn_usb_phy_sels, base + 0xb180));
301 	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
303 	       imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
305 	       imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
307 	       imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
309 	       imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
311 	       imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
313 	       imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
315 	       imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
317 	       imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
319 	       imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
321 	       imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
323 	       imx_clk_gate4("qspi_root_clk", "qspi", base + 0x42f0, 0));
325 	       imx_clk_gate2_shared2("nand_root_clk", "nand", base + 0x4300, 0, &share_count_nand));
328 				     "nand_usdhc_bus", base + 0x4300, 0,
331 		imx_clk_gate4("usb1_ctrl_root_clk", "usb_bus", base + 0x44d0, 0));
337 	       base + 0xa980));
340 	       base + 0xaa00));
343 	       base + 0xaa80));
346 	       base + 0x40a0, 0));
348 	       imx8m_clk_composite("pwm1", imx8mn_pwm1_sels, base + 0xb380));
350 	       imx8m_clk_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400));
352 	       imx8m_clk_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480));
354 	       imx8m_clk_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500));
356 	       imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
358 	       imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
360 	       imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
362 	       imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
367 	       imx8m_clk_composite("ecspi1", imx8mn_ecspi1_sels, base + 0xb280));
369 	       imx8m_clk_composite("ecspi2", imx8mn_ecspi2_sels, base + 0xb300));
371 	       imx8m_clk_composite("ecspi3", imx8mn_ecspi3_sels, base + 0xc180));
373 	       imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, 0));
375 	       imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, 0));
377 	       imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, 0));