1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2020 Microchip Technology Inc.
4 * Padmarao Begari <padmarao.begari@microchip.com>
5 */
6#ifndef __MICROCHIP_MPFS_CLK_H
7#define __MICROCHIP_MPFS_CLK_H
8
9#include <linux/clk-provider.h>
10/**
11 * mpfs_clk_register_cfgs() - register configuration clocks
12 *
13 * @base: base address of the mpfs system register.
14 * @parent: a pointer to parent clock.
15 * Return: zero on success, or a negative error code.
16 */
17int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
18/**
19 * mpfs_clk_register_msspll() - register the mss pll
20 *
21 * @base: base address of the mpfs system register.
22 * @parent: a pointer to parent clock.
23 * Return: zero on success, or a negative error code.
24 */
25int mpfs_clk_register_msspll(void __iomem *base, struct clk *parent);
26/**
27 * mpfs_clk_register_periphs() - register peripheral clocks
28 *
29 * @base: base address of the mpfs system register.
30 * @dev: udevice representing the clock controller.
31 * Return: zero on success, or a negative error code.
32 */
33int mpfs_clk_register_periphs(void __iomem *base, struct udevice *dev);
34/**
35 * divider_get_val() - get the clock divider value
36 *
37 * @rate: requested clock rate.
38 * @parent_rate: parent clock rate.
39 * @table: a pointer to clock divider table.
40 * @width: width of the divider bit field.
41 * @flags: common clock framework flags.
42 * Return: divider value on success, or a negative error code.
43 */
44int divider_get_val(unsigned long rate, unsigned long parent_rate,
45		    const struct clk_div_table *table,
46		    u8 width, unsigned long flags);
47
48#endif	/* __MICROCHIP_MPFS_CLK_H */
49