1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014 Google, Inc
4 */
5
6#define LOG_CATEGORY	UCLASS_PCH
7
8#include <common.h>
9#include <dm.h>
10#include <log.h>
11#include <pch.h>
12
13#define GPIO_BASE	0x48
14#define IO_BASE		0x4c
15#define SBASE_ADDR	0x54
16
17static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
18{
19	uint32_t sbase_addr;
20
21	dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
22	*sbasep = sbase_addr & 0xfffffe00;
23
24	return 0;
25}
26
27static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
28{
29	u32 base;
30
31	/*
32	 * GPIO_BASE moved to its current offset with ICH6, but prior to
33	 * that it was unused (or undocumented). Check that it looks
34	 * okay: not all ones or zeros.
35	 *
36	 * Note we don't need check bit0 here, because the Tunnel Creek
37	 * GPIO base address register bit0 is reserved (read returns 0),
38	 * while on the Ivybridge the bit0 is used to indicate it is an
39	 * I/O space.
40	 */
41	dm_pci_read_config32(dev, GPIO_BASE, &base);
42	if (base == 0x00000000 || base == 0xffffffff) {
43		log_debug("unexpected BASE value\n");
44		return -ENODEV;
45	}
46
47	/*
48	 * Okay, I guess we're looking at the right device. The actual
49	 * GPIO registers are in the PCI device's I/O space, starting
50	 * at the offset that we just read. Bit 0 indicates that it's
51	 * an I/O address, not a memory address, so mask that off.
52	 */
53	*gbasep = base & 1 ? base & ~3 : base & ~15;
54
55	return 0;
56}
57
58static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
59{
60	u32 base;
61
62	dm_pci_read_config32(dev, IO_BASE, &base);
63	if (base == 0x00000000 || base == 0xffffffff) {
64		log_debug("unexpected BASE value\n");
65		return -ENODEV;
66	}
67
68	*iobasep = base & 1 ? base & ~3 : base & ~15;
69
70	return 0;
71}
72
73static const struct pch_ops pch9_ops = {
74	.get_spi_base	= pch9_get_spi_base,
75	.get_gpio_base	= pch9_get_gpio_base,
76	.get_io_base	= pch9_get_io_base,
77};
78
79static const struct udevice_id pch9_ids[] = {
80	{ .compatible = "intel,pch9" },
81	{ }
82};
83
84U_BOOT_DRIVER(pch9_drv) = {
85	.name		= "intel-pch9",
86	.id		= UCLASS_PCH,
87	.of_match	= pch9_ids,
88	.ops		= &pch9_ops,
89};
90