Searched refs:way (Results 1 - 8 of 8) sorted by relevance
/u-boot/arch/arc/include/asm/ |
H A D | arc-bcr.h | 30 unsigned int pad:24, way:2, lsz:2, sz:4; member in struct:bcr_slc_cfg::__anon2 32 unsigned int sz:4, lsz:2, way:2, pad:24;
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/u-boot/arch/arm/cpu/armv7/ |
H A D | cache_v7_asm.S | 45 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 46 clz r5, r4 @ find bit position of way size increment 52 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 54 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 58 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 61 subs r4, r4, #1 @ decrement the way 115 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 116 clz r5, r4 @ find bit position of way size increment 122 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11 124 THUMB( orr r11, r10, r6 ) @ factor way an [all...] |
H A D | psci.S | 191 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 192 clz r5, r4 @ find bit position of way size increment 198 orr r11, r10, r4, lsl r5 @ factor way and cache number into r11 200 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 203 subs r4, r4, #1 @ decrement the way
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/u-boot/arch/arm/mach-npcm/npcm7xx/ |
H A D | l2_cache_pl310_init.S | 50 STR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C 52 LDR r1, [r0,#0x77C] @ invalidate by way register at offset 0x77C
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/u-boot/arch/arm/mach-uniphier/arm32/ |
H A D | lowlevel_init.S | 87 #define BOOT_RAM_WAYS (0x00000100) @ way 8 101 /* Touch to zero for the boot way */
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/u-boot/arch/arm/mach-omap2/ |
H A D | config_secure.mk | 101 # order to secure them in some way
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/u-boot/drivers/net/ |
H A D | mvpp2.c | 1205 u32 way; member in struct:mvpp2_cls_lookup_entry 2466 val = (le->way << MVPP2_CLS_LKP_INDEX_WAY_OFFS) | le->lkpid; 2492 le.way = 0; 2495 le.way = 1; 2505 /* Set way for the port */ 2511 * according to the way and lkpid. 2514 le.way = 0;
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/u-boot/arch/powerpc/include/asm/ |
H A D | immap_85xx.h | 1206 u32 way; /* partition way */ member in struct:cpc_corenet::__anon48 1252 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ 2680 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */ 2684 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */ 2688 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */ 2692 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */ 2696 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */ 2700 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */ 2704 u32 l2pwr6; /* 0x26c L2 cache partitioning way registe [all...] |
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