#
2f420f13 |
|
27-Nov-2022 |
Tom Rini <trini@konsulko.com> |
net: tsec: Remove non-DM_ETH support code As DM_ETH is required for all network drivers, it's now safe to remove the non-DM_ETH support code. Doing this removes some board support code which was also unused. Finally, this removes some CONFIG symbols that otherwise needed to be migrated to Kconfig, but were unused in code now. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
65cc0e2a |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_* to CFG_SYS_* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
ecc8d425 |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI* The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
3408d96e |
|
16-Nov-2022 |
Tom Rini <trini@konsulko.com> |
Remove unused symbols This commit removes the following unused symbols: CONFIG_SYS_NVRAM_BASE_ADDR CONFIG_SYS_NVRAM_SIZE CONFIG_SYS_PAXE_BASE CONFIG_SYS_PCCNT CONFIG_SYS_PCDAT CONFIG_SYS_PCDDR CONFIG_SYS_PCI1_ADDR CONFIG_SYS_PCI2_ADDR CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_SIZE CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_SIZE CONFIG_SYS_PCIE3_ADDR CONFIG_SYS_PCIE4_ADDR CONFIG_SYS_PCIE3_IO_PHYS CONFIG_SYS_PCIE3_IO_VIRT CONFIG_SYS_PCIE4_IO_PHYS CONFIG_SYS_PCIE4_IO_VIRT CONFIG_SYS_PLL_SETTLING_TIME CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_SP_CENA_SIZE CONFIG_SYS_RCAR_I2C0_BASE CONFIG_SYS_RCAR_I2C1_BASE CONFIG_SYS_RCAR_I2C2_BASE CONFIG_SYS_RCAR_I2C3_BASE CONFIG_SYS_SATA CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_SGMII_REFCLK_MHZ CONFIG_SYS_SGMII_LINERATE_MHZ CONFIG_SYS_SGMII_RATESCALE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI0_BASE CONFIG_SYS_SH_SDHI1_BASE CONFIG_SYS_SH_SDHI2_BASE CONFIG_SYS_SH_SDHI3_BASE CONFIG_SYS_SPI_ST_ENABLE_WP_PIN CONFIG_SYS_SPI_U_BOOT_SIZE CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT CONFIG_SYS_VCXK_BASE CONFIG_SYS_VCXK_DEFAULT_LINEALIGN CONFIG_SYS_VCXK_DOUBLEBUFFERED CONFIG_SYS_VCXK_ENABLE_DDR CONFIG_SYS_VCXK_ENABLE_PIN CONFIG_SYS_VCXK_ENABLE_PORT CONFIG_SYS_VCXK_INVERT_DDR CONFIG_SYS_VCXK_INVERT_PIN CONFIG_SYS_VCXK_INVERT_PORT CONFIG_SYS_VCXK_REQUEST_DDR CONFIG_SYS_VCXK_REQUEST_PIN CONFIG_SYS_VCXK_REQUEST_PORT CONFIG_SYS_VSC7385_BR_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5155207a |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8b549c0b |
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31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3db7b2bb |
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22-Feb-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Remove unused MPC8540/60ADS code Remove some code, primarily CPM2 related, that is now unused since the removal of MPC8540/60ADS. Fixes 3913191c8a6b ("powerpc: mpc8540ads: mpc8560ads: Drop support for MPC8540/60ADS") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
ec6b37ce |
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23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed7fe2be |
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14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove xpedite boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this includes the last ARCH_MPC8572 platform, remove that as well. Cc: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peter Tyser <ptyser@xes-inc.com> |
#
80696893 |
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14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8568MDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_MPC8568 platform, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6c3d9933 |
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14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
98898601 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8555CDS boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_MPC8555 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a8571337 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8541CDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
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20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
3238d934 |
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20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove ARCH_P1022 support With the last of the ARCH_P1022 platforms removed, finish removing the rest of the platform support. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2322b956 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T2081QDS board and ARCH_T2081 support This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. It is also the only ARCH_T2081 board so remove that support as well. Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f94cbb5b |
|
25-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio' Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2cc6071e |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8569MDS board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db148f2a |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c00d0012 |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fbe44dd1 |
|
05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com> |
#
08a37fd1 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cdb72c52 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
26bc57da |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
652a7bbd |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0f3d80e9 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5449c98a |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d737010 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
b41f192b |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros. |
#
3006ebc3 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4593637b |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4167a67d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a990799d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
41c7b7b1 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
46d9fc0b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
2f8b8126 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
83b9bea1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9bb1d6bc |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
feb9e25b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7d5f9f84 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
c8f48474 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
23b36a7d |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d07c3843 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3c3d8ab5 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3aff3082 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7f825218 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24ad75ae |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4fd64746 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
115d60c0 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com> |
#
281ed4c7 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> |
#
15a6d496 |
|
17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f3dbf1f0 |
|
01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com> |
#
07d31f8f |
|
25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec2c81c5 |
|
25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
f698e9f3 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8225b2fd |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
a2e225e6 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5818643b |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cc19c25e |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7cad2e38 |
|
29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b9eebfad |
|
15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
48ef0d2a |
|
09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e55782ec |
|
27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
377ffcfa |
|
05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b6808cd8 |
|
28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com> |
#
5122dfae |
|
25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0c12a159 |
|
15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5aef4c86 |
|
26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c3678b09 |
|
28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com> |
#
2a44efeb |
|
21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
bf4699db |
|
30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7af9a074 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb07c0a1 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5b7672fc |
|
27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com> |
#
b135991a |
|
17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> |
#
629d6b32 |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
82a55c1e |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0b66513b |
|
22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com> |
#
9a17eb5b |
|
18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com> |
#
5614e71b |
|
30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com> |
#
8f9fe660 |
|
23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> |
#
2967af68 |
|
17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com> |
#
77354e9d |
|
12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
133fbfa9 |
|
16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com> |
#
ce746fe0 |
|
02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
9dee205d |
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05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
3b75e982 |
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04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
6fbe9889 |
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02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com> |
#
f9d379a7 |
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01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
b3831020 |
|
25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
69fdf900 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5870fe44 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
8bd00c94 |
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20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f6981439 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5f208d11 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b6240846 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1e501f91 |
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25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
45c18853 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99d7b0a4 |
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11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
ada961e2 |
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24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5e95e2d8 |
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23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
35fe948e |
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23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e1dbdd81 |
|
23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b25f6de7 |
|
01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d607b968 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e76cd5d4 |
|
23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> |
#
d2404141 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9e758758 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f311838d |
|
08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d1001e3f |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
fd3cebd0 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
92230d49 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f8f85b04 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9a653a98 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f77329cf |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
6d2b9da1 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
4905443f |
|
05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e389a377 |
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05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
a4c66509 |
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17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
50d96e95 |
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17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1ca8690d |
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17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
3e978f5d |
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14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
055ce080 |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99abf7de |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
be7bebea |
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10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
81fa73ba |
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08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
19a8dbdc |
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24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
5ffa88ec |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> |
#
7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> |
#
9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6b3a8d00 |
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10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fe1a1da0 |
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04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
c916d7c9 |
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13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f110fe94 |
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20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f68d3063 |
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14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
86221f09 |
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12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
e02aea61 |
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08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
df8af0b4 |
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31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
2bad42a0 |
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09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
4b77047c |
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22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
b93f81a4 |
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03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4aa8405c |
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27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a52d2f81 |
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11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
24995d82 |
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20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
67a719da |
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03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d789b5f5 |
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20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
28747f9b |
|
20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d2a9568c |
|
09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17028be2 |
|
17-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
868da593 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1d2c2a62 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
3c6a22b9 |
|
23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ed062e0f |
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17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
680c613a |
|
09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a37c36f4 |
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14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ebd7cb0b |
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02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
9ab87d04 |
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28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
99d9c07e |
|
08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f51cdaf1 |
|
17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
22f292c7 |
|
31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6e37a044 |
|
19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
0c955daf |
|
14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1231c498 |
|
07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17d90f31 |
|
04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ab48ca1a |
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10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a47a12be |
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15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
6cc04547 |
|
28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
5155207a |
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28-Oct-2022 |
Tom Rini <trini@konsulko.com> |
global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespace Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8b549c0b |
|
31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3db7b2bb |
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22-Feb-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Remove unused MPC8540/60ADS code Remove some code, primarily CPM2 related, that is now unused since the removal of MPC8540/60ADS. Fixes 3913191c8a6b ("powerpc: mpc8540ads: mpc8560ads: Drop support for MPC8540/60ADS") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
ec6b37ce |
|
23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed7fe2be |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove xpedite boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this includes the last ARCH_MPC8572 platform, remove that as well. Cc: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peter Tyser <ptyser@xes-inc.com> |
#
80696893 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8568MDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_MPC8568 platform, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6c3d9933 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
98898601 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8555CDS boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_MPC8555 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a8571337 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8541CDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
3238d934 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove ARCH_P1022 support With the last of the ARCH_P1022 platforms removed, finish removing the rest of the platform support. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2322b956 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T2081QDS board and ARCH_T2081 support This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. It is also the only ARCH_T2081 board so remove that support as well. Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f94cbb5b |
|
25-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio' Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2cc6071e |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8569MDS board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db148f2a |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c00d0012 |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fbe44dd1 |
|
05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com> |
#
08a37fd1 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cdb72c52 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
26bc57da |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
652a7bbd |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0f3d80e9 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5449c98a |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d737010 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
b41f192b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros. |
#
3006ebc3 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4593637b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4167a67d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a990799d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
41c7b7b1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
46d9fc0b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
2f8b8126 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
83b9bea1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9bb1d6bc |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
feb9e25b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7d5f9f84 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
c8f48474 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
23b36a7d |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d07c3843 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3c3d8ab5 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3aff3082 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7f825218 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24ad75ae |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4fd64746 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
115d60c0 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com> |
#
281ed4c7 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> |
#
15a6d496 |
|
17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f3dbf1f0 |
|
01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com> |
#
07d31f8f |
|
25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec2c81c5 |
|
25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
f698e9f3 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8225b2fd |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
a2e225e6 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5818643b |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cc19c25e |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7cad2e38 |
|
29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b9eebfad |
|
15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
48ef0d2a |
|
09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e55782ec |
|
27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
377ffcfa |
|
05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b6808cd8 |
|
28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com> |
#
5122dfae |
|
25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0c12a159 |
|
15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5aef4c86 |
|
26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c3678b09 |
|
28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com> |
#
2a44efeb |
|
21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
bf4699db |
|
30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7af9a074 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb07c0a1 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5b7672fc |
|
27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com> |
#
b135991a |
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17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> |
#
629d6b32 |
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22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
82a55c1e |
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22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
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0b66513b |
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22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com> |
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9a17eb5b |
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18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com> |
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5614e71b |
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30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com> |
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8f9fe660 |
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23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> |
#
2967af68 |
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17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com> |
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77354e9d |
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12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
133fbfa9 |
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16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com> |
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ce746fe0 |
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02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
9dee205d |
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05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
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3b75e982 |
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04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> |
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6fbe9889 |
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02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com> |
#
f9d379a7 |
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01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
b3831020 |
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25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
69fdf900 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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5870fe44 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
8bd00c94 |
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20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f6981439 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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5f208d11 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b6240846 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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1e501f91 |
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25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
45c18853 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99d7b0a4 |
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11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
ada961e2 |
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24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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5e95e2d8 |
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23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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35fe948e |
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23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e1dbdd81 |
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23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b25f6de7 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d607b968 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e76cd5d4 |
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23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> |
#
d2404141 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9e758758 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f311838d |
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08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d1001e3f |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
fd3cebd0 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
92230d49 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f8f85b04 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9a653a98 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f77329cf |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
6d2b9da1 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
4905443f |
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05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e389a377 |
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05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
a4c66509 |
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17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
50d96e95 |
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17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1ca8690d |
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17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
3e978f5d |
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14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
055ce080 |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99abf7de |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
be7bebea |
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10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
81fa73ba |
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08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
19a8dbdc |
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24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
5ffa88ec |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> |
#
7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> |
#
9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6b3a8d00 |
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10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fe1a1da0 |
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04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
c916d7c9 |
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13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f110fe94 |
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20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f68d3063 |
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14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
86221f09 |
|
12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
e02aea61 |
|
08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
df8af0b4 |
|
31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
2bad42a0 |
|
09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
4b77047c |
|
22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
b93f81a4 |
|
03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4aa8405c |
|
27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a52d2f81 |
|
11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
24995d82 |
|
20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
67a719da |
|
03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d789b5f5 |
|
20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
28747f9b |
|
20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d2a9568c |
|
09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17028be2 |
|
17-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
868da593 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1d2c2a62 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
3c6a22b9 |
|
23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ed062e0f |
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17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
680c613a |
|
09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a37c36f4 |
|
14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ebd7cb0b |
|
02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
9ab87d04 |
|
28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
99d9c07e |
|
08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f51cdaf1 |
|
17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
22f292c7 |
|
31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6e37a044 |
|
19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
0c955daf |
|
14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1231c498 |
|
07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17d90f31 |
|
04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ab48ca1a |
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10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
8b549c0b |
|
31-Jul-2022 |
Tom Rini <trini@konsulko.com> |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al This removes the following symbols: CONFIG_SYS_FSL_DSPI_BE CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET CONFIG_SYS_FSL_DSP_DDR_ADDR CONFIG_SYS_FSL_DSP_M2_RAM_ADDR CONFIG_SYS_FSL_DSP_M3_RAM_ADDR CONFIG_SYS_FSL_ERRATUM_A008751 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT CONFIG_SYS_FSL_ESDHC_NUM CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET CONFIG_SYS_FSL_ISBC_VER CONFIG_SYS_FSL_QSPI_LE CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR CONFIG_SYS_FSL_SRDS_NUM_PLLS CONFIG_SYS_FSL_WDOG_BE CONFIG_SYS_GP1DIR CONFIG_SYS_GP1ODR CONFIG_SYS_GP2DIR CONFIG_SYS_GP2ODR CONFIG_SYS_HALT_BEFOR_RAM_JUMP CONFIG_SYS_HMI_BASE FSL_QSPI_FLASH_NUM FSL_QSPI_FLASH_SIZE Signed-off-by: Tom Rini <trini@konsulko.com> |
#
3db7b2bb |
|
22-Feb-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Remove unused MPC8540/60ADS code Remove some code, primarily CPM2 related, that is now unused since the removal of MPC8540/60ADS. Fixes 3913191c8a6b ("powerpc: mpc8540ads: mpc8560ads: Drop support for MPC8540/60ADS") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
ec6b37ce |
|
23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed7fe2be |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove xpedite boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this includes the last ARCH_MPC8572 platform, remove that as well. Cc: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peter Tyser <ptyser@xes-inc.com> |
#
80696893 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8568MDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_MPC8568 platform, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6c3d9933 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
98898601 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8555CDS boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_MPC8555 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a8571337 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8541CDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
3238d934 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove ARCH_P1022 support With the last of the ARCH_P1022 platforms removed, finish removing the rest of the platform support. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2322b956 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T2081QDS board and ARCH_T2081 support This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. It is also the only ARCH_T2081 board so remove that support as well. Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f94cbb5b |
|
25-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio' Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2cc6071e |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8569MDS board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db148f2a |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c00d0012 |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fbe44dd1 |
|
05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com> |
#
08a37fd1 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cdb72c52 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
26bc57da |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
652a7bbd |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0f3d80e9 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5449c98a |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d737010 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
b41f192b |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros. |
#
3006ebc3 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4593637b |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4167a67d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a990799d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
41c7b7b1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
46d9fc0b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
2f8b8126 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
83b9bea1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9bb1d6bc |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
feb9e25b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7d5f9f84 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
c8f48474 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
23b36a7d |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d07c3843 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3c3d8ab5 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3aff3082 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7f825218 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24ad75ae |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4fd64746 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
115d60c0 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com> |
#
281ed4c7 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> |
#
15a6d496 |
|
17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f3dbf1f0 |
|
01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com> |
#
07d31f8f |
|
25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec2c81c5 |
|
25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
f698e9f3 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8225b2fd |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
a2e225e6 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5818643b |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cc19c25e |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7cad2e38 |
|
29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b9eebfad |
|
15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
48ef0d2a |
|
09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e55782ec |
|
27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
377ffcfa |
|
05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b6808cd8 |
|
28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com> |
#
5122dfae |
|
25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0c12a159 |
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15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5aef4c86 |
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26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c3678b09 |
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28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com> |
#
2a44efeb |
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21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
bf4699db |
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30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7af9a074 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb07c0a1 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5b7672fc |
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27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com> |
#
b135991a |
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17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> |
#
629d6b32 |
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22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
82a55c1e |
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22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0b66513b |
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22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com> |
#
9a17eb5b |
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18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com> |
#
5614e71b |
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30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com> |
#
8f9fe660 |
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23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> |
#
2967af68 |
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17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com> |
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77354e9d |
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12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
133fbfa9 |
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16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com> |
#
ce746fe0 |
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02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
9dee205d |
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05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
3b75e982 |
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04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
6fbe9889 |
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02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com> |
#
f9d379a7 |
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01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
b3831020 |
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25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
69fdf900 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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5870fe44 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
8bd00c94 |
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20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f6981439 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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5f208d11 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b6240846 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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1e501f91 |
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25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
45c18853 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99d7b0a4 |
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11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
ada961e2 |
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24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5e95e2d8 |
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23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
35fe948e |
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23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e1dbdd81 |
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23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b25f6de7 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d607b968 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e76cd5d4 |
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23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> |
#
d2404141 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9e758758 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f311838d |
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08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d1001e3f |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
fd3cebd0 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
92230d49 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f8f85b04 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9a653a98 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f77329cf |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
6d2b9da1 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
4905443f |
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05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e389a377 |
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05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
a4c66509 |
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17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
50d96e95 |
|
17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1ca8690d |
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17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
3e978f5d |
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14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
055ce080 |
|
14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99abf7de |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
be7bebea |
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10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
81fa73ba |
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08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
19a8dbdc |
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24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
5ffa88ec |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> |
#
7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> |
#
9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6b3a8d00 |
|
10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7065b7d4 |
|
15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fe1a1da0 |
|
04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
c916d7c9 |
|
13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f110fe94 |
|
20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f68d3063 |
|
14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
86221f09 |
|
12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
e02aea61 |
|
08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
df8af0b4 |
|
31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
2bad42a0 |
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09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
4b77047c |
|
22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
b93f81a4 |
|
03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4aa8405c |
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27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a52d2f81 |
|
11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
24995d82 |
|
20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
67a719da |
|
03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d789b5f5 |
|
20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
28747f9b |
|
20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d2a9568c |
|
09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17028be2 |
|
17-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
868da593 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1d2c2a62 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
3c6a22b9 |
|
23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ed062e0f |
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17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
680c613a |
|
09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a37c36f4 |
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14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ebd7cb0b |
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02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
9ab87d04 |
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28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
99d9c07e |
|
08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f51cdaf1 |
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17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
22f292c7 |
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31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6e37a044 |
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19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
0c955daf |
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14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1231c498 |
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07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17d90f31 |
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04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ab48ca1a |
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10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
3db7b2bb |
|
22-Feb-2022 |
Tom Rini <trini@konsulko.com> |
powerpc: Remove unused MPC8540/60ADS code Remove some code, primarily CPM2 related, that is now unused since the removal of MPC8540/60ADS. Fixes 3913191c8a6b ("powerpc: mpc8540ads: mpc8560ads: Drop support for MPC8540/60ADS") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
ec6b37ce |
|
23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed7fe2be |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove xpedite boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this includes the last ARCH_MPC8572 platform, remove that as well. Cc: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peter Tyser <ptyser@xes-inc.com> |
#
80696893 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8568MDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_MPC8568 platform, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6c3d9933 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
98898601 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8555CDS boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_MPC8555 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a8571337 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8541CDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
3238d934 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove ARCH_P1022 support With the last of the ARCH_P1022 platforms removed, finish removing the rest of the platform support. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2322b956 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T2081QDS board and ARCH_T2081 support This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. It is also the only ARCH_T2081 board so remove that support as well. Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f94cbb5b |
|
25-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio' Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2cc6071e |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8569MDS board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db148f2a |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c00d0012 |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fbe44dd1 |
|
05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com> |
#
08a37fd1 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cdb72c52 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
26bc57da |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
652a7bbd |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0f3d80e9 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5449c98a |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d737010 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
b41f192b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros. |
#
3006ebc3 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4593637b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4167a67d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a990799d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
41c7b7b1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
46d9fc0b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
2f8b8126 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
83b9bea1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9bb1d6bc |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
feb9e25b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7d5f9f84 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
c8f48474 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
23b36a7d |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d07c3843 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3c3d8ab5 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3aff3082 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7f825218 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24ad75ae |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4fd64746 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
115d60c0 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com> |
#
281ed4c7 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> |
#
15a6d496 |
|
17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f3dbf1f0 |
|
01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com> |
#
07d31f8f |
|
25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec2c81c5 |
|
25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
f698e9f3 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8225b2fd |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
a2e225e6 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5818643b |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cc19c25e |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7cad2e38 |
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29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b9eebfad |
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15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
48ef0d2a |
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09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e55782ec |
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27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
377ffcfa |
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05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b6808cd8 |
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28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com> |
#
5122dfae |
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25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0c12a159 |
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15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5aef4c86 |
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26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c3678b09 |
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28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com> |
#
2a44efeb |
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21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
bf4699db |
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30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7af9a074 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb07c0a1 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5b7672fc |
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27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com> |
#
b135991a |
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17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> |
#
629d6b32 |
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22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
82a55c1e |
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22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0b66513b |
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22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com> |
#
9a17eb5b |
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18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com> |
#
5614e71b |
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30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com> |
#
8f9fe660 |
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23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> |
#
2967af68 |
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17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com> |
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77354e9d |
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12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
133fbfa9 |
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16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com> |
#
ce746fe0 |
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02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
9dee205d |
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05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
3b75e982 |
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04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
6fbe9889 |
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02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com> |
#
f9d379a7 |
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01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
b3831020 |
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25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
69fdf900 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5870fe44 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
8bd00c94 |
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20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f6981439 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5f208d11 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b6240846 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1e501f91 |
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25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
45c18853 |
|
25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99d7b0a4 |
|
11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
ada961e2 |
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24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5e95e2d8 |
|
23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
35fe948e |
|
23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e1dbdd81 |
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23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b25f6de7 |
|
01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d607b968 |
|
01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e76cd5d4 |
|
23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> |
#
d2404141 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9e758758 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f311838d |
|
08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d1001e3f |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
fd3cebd0 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
92230d49 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f8f85b04 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9a653a98 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f77329cf |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
6d2b9da1 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
4905443f |
|
05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e389a377 |
|
05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
a4c66509 |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
50d96e95 |
|
17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1ca8690d |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
3e978f5d |
|
14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
055ce080 |
|
14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99abf7de |
|
14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
be7bebea |
|
10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
81fa73ba |
|
08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
19a8dbdc |
|
24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
5ffa88ec |
|
07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> |
#
7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> |
#
9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6b3a8d00 |
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10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fe1a1da0 |
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04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
c916d7c9 |
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13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f110fe94 |
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20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f68d3063 |
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14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
86221f09 |
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12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
e02aea61 |
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08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
df8af0b4 |
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31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
2bad42a0 |
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09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
4b77047c |
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22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
b93f81a4 |
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03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4aa8405c |
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27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a52d2f81 |
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11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
24995d82 |
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20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
67a719da |
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03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d789b5f5 |
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20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
28747f9b |
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20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d2a9568c |
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09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17028be2 |
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17-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
868da593 |
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13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1d2c2a62 |
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13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
3c6a22b9 |
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23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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ed062e0f |
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17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
680c613a |
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09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a37c36f4 |
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14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ebd7cb0b |
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02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
9ab87d04 |
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28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
99d9c07e |
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08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f51cdaf1 |
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17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
22f292c7 |
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31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6e37a044 |
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19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
0c955daf |
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14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1231c498 |
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07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17d90f31 |
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04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ab48ca1a |
|
10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
ec6b37ce |
|
23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed7fe2be |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove xpedite boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this includes the last ARCH_MPC8572 platform, remove that as well. Cc: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peter Tyser <ptyser@xes-inc.com> |
#
80696893 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8568MDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_MPC8568 platform, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6c3d9933 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
98898601 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8555CDS boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_MPC8555 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a8571337 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8541CDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
3238d934 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove ARCH_P1022 support With the last of the ARCH_P1022 platforms removed, finish removing the rest of the platform support. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2322b956 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T2081QDS board and ARCH_T2081 support This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. It is also the only ARCH_T2081 board so remove that support as well. Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f94cbb5b |
|
25-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio' Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2cc6071e |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8569MDS board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db148f2a |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c00d0012 |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fbe44dd1 |
|
05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com> |
#
08a37fd1 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cdb72c52 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
26bc57da |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
652a7bbd |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0f3d80e9 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5449c98a |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d737010 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
b41f192b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros. |
#
3006ebc3 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4593637b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4167a67d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a990799d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
41c7b7b1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
46d9fc0b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
2f8b8126 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
83b9bea1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9bb1d6bc |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
feb9e25b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7d5f9f84 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
c8f48474 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
23b36a7d |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d07c3843 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3c3d8ab5 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3aff3082 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7f825218 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24ad75ae |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4fd64746 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
115d60c0 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com> |
#
281ed4c7 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> |
#
15a6d496 |
|
17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f3dbf1f0 |
|
01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com> |
#
07d31f8f |
|
25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec2c81c5 |
|
25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
f698e9f3 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8225b2fd |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
a2e225e6 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5818643b |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cc19c25e |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7cad2e38 |
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29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b9eebfad |
|
15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
48ef0d2a |
|
09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e55782ec |
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27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
377ffcfa |
|
05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b6808cd8 |
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28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com> |
#
5122dfae |
|
25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0c12a159 |
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15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5aef4c86 |
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26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c3678b09 |
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28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com> |
#
2a44efeb |
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21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
bf4699db |
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30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7af9a074 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb07c0a1 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5b7672fc |
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27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com> |
#
b135991a |
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17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> |
#
629d6b32 |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
82a55c1e |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0b66513b |
|
22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com> |
#
9a17eb5b |
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18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com> |
#
5614e71b |
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30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com> |
#
8f9fe660 |
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23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> |
#
2967af68 |
|
17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com> |
#
77354e9d |
|
12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
133fbfa9 |
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16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com> |
#
ce746fe0 |
|
02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
9dee205d |
|
05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
3b75e982 |
|
04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
6fbe9889 |
|
02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com> |
#
f9d379a7 |
|
01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
b3831020 |
|
25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
69fdf900 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5870fe44 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
8bd00c94 |
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20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f6981439 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5f208d11 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b6240846 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1e501f91 |
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25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
45c18853 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99d7b0a4 |
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11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
ada961e2 |
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24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5e95e2d8 |
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23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
35fe948e |
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23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e1dbdd81 |
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23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b25f6de7 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d607b968 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e76cd5d4 |
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23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> |
#
d2404141 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9e758758 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f311838d |
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08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d1001e3f |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
fd3cebd0 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
92230d49 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f8f85b04 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9a653a98 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f77329cf |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
6d2b9da1 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
4905443f |
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05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e389a377 |
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05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
a4c66509 |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
50d96e95 |
|
17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1ca8690d |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
3e978f5d |
|
14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
055ce080 |
|
14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99abf7de |
|
14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
be7bebea |
|
10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
81fa73ba |
|
08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
19a8dbdc |
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24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
5ffa88ec |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> |
#
7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> |
#
9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6b3a8d00 |
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10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fe1a1da0 |
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04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
c916d7c9 |
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13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f110fe94 |
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20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f68d3063 |
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14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
86221f09 |
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12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
e02aea61 |
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08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
df8af0b4 |
|
31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
2bad42a0 |
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09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
4b77047c |
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22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
b93f81a4 |
|
03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4aa8405c |
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27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a52d2f81 |
|
11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
24995d82 |
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20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
67a719da |
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03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d789b5f5 |
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20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
28747f9b |
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20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d2a9568c |
|
09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17028be2 |
|
17-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
868da593 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1d2c2a62 |
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13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
3c6a22b9 |
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23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ed062e0f |
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17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
680c613a |
|
09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a37c36f4 |
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14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ebd7cb0b |
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02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
9ab87d04 |
|
28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
99d9c07e |
|
08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f51cdaf1 |
|
17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
22f292c7 |
|
31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6e37a044 |
|
19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
0c955daf |
|
14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1231c498 |
|
07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17d90f31 |
|
04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ab48ca1a |
|
10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
ec6b37ce |
|
23-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T4160RDB board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_T4160 platform, remove that support as well. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
ed7fe2be |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove xpedite boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this includes the last ARCH_MPC8572 platform, remove that as well. Cc: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peter Tyser <ptyser@xes-inc.com> |
#
80696893 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8568MDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the last ARCH_MPC8568 platform, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
6c3d9933 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_T1023 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
98898601 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8555CDS boards These boards have not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove them. As this is the only ARCH_MPC8555 platform left, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a8571337 |
|
14-May-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8541CDS board This board has not been converted to CONFIG_DM_PCI by the deadline and is also missing conversion to CONFIG_DM. Remove it. As this is the only MPC8541 target left, remove that architecture support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a99dab1d |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
3238d934 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove ARCH_P1022 support With the last of the ARCH_P1022 platforms removed, finish removing the rest of the platform support. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2322b956 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T2081QDS board and ARCH_T2081 support This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. It is also the only ARCH_T2081 board so remove that support as well. Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f94cbb5b |
|
25-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio' Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2cc6071e |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8569MDS board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db148f2a |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c00d0012 |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fbe44dd1 |
|
05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com> |
#
08a37fd1 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cdb72c52 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
26bc57da |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
652a7bbd |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0f3d80e9 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5449c98a |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d737010 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
b41f192b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros. |
#
3006ebc3 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4593637b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4167a67d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a990799d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
41c7b7b1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
46d9fc0b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
2f8b8126 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
83b9bea1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9bb1d6bc |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
feb9e25b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7d5f9f84 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
c8f48474 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
23b36a7d |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d07c3843 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3c3d8ab5 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3aff3082 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7f825218 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24ad75ae |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4fd64746 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
115d60c0 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com> |
#
281ed4c7 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> |
#
15a6d496 |
|
17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f3dbf1f0 |
|
01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com> |
#
07d31f8f |
|
25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec2c81c5 |
|
25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
f698e9f3 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8225b2fd |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
a2e225e6 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5818643b |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cc19c25e |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7cad2e38 |
|
29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b9eebfad |
|
15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
48ef0d2a |
|
09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e55782ec |
|
27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
377ffcfa |
|
05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b6808cd8 |
|
28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com> |
#
5122dfae |
|
25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0c12a159 |
|
15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5aef4c86 |
|
26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c3678b09 |
|
28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com> |
#
2a44efeb |
|
21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
bf4699db |
|
30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7af9a074 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb07c0a1 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5b7672fc |
|
27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com> |
#
b135991a |
|
17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> |
#
629d6b32 |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
82a55c1e |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0b66513b |
|
22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com> |
#
9a17eb5b |
|
18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com> |
#
5614e71b |
|
30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com> |
#
8f9fe660 |
|
23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> |
#
2967af68 |
|
17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com> |
#
77354e9d |
|
12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
133fbfa9 |
|
16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com> |
#
ce746fe0 |
|
02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
9dee205d |
|
05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
3b75e982 |
|
04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
6fbe9889 |
|
02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com> |
#
f9d379a7 |
|
01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
b3831020 |
|
25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
69fdf900 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5870fe44 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
8bd00c94 |
|
20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f6981439 |
|
25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5f208d11 |
|
25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b6240846 |
|
25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1e501f91 |
|
25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
45c18853 |
|
25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99d7b0a4 |
|
11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
ada961e2 |
|
24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5e95e2d8 |
|
23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
35fe948e |
|
23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e1dbdd81 |
|
23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b25f6de7 |
|
01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d607b968 |
|
01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e76cd5d4 |
|
23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> |
#
d2404141 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9e758758 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f311838d |
|
08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d1001e3f |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
fd3cebd0 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
92230d49 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f8f85b04 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9a653a98 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f77329cf |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
6d2b9da1 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
4905443f |
|
05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e389a377 |
|
05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
a4c66509 |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
50d96e95 |
|
17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1ca8690d |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
3e978f5d |
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14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
055ce080 |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99abf7de |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
be7bebea |
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10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
81fa73ba |
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08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
19a8dbdc |
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24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
5ffa88ec |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> |
#
7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> |
#
9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6b3a8d00 |
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10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fe1a1da0 |
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04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
c916d7c9 |
|
13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f110fe94 |
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20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f68d3063 |
|
14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
86221f09 |
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12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
e02aea61 |
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08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
df8af0b4 |
|
31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
2bad42a0 |
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09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
4b77047c |
|
22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
b93f81a4 |
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03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4aa8405c |
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27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a52d2f81 |
|
11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
24995d82 |
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20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
67a719da |
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03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d789b5f5 |
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20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
28747f9b |
|
20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d2a9568c |
|
09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17028be2 |
|
17-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
868da593 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1d2c2a62 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
3c6a22b9 |
|
23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ed062e0f |
|
17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
680c613a |
|
09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a37c36f4 |
|
14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ebd7cb0b |
|
02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
9ab87d04 |
|
28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
99d9c07e |
|
08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f51cdaf1 |
|
17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
22f292c7 |
|
31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6e37a044 |
|
19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
0c955daf |
|
14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1231c498 |
|
07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17d90f31 |
|
04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ab48ca1a |
|
10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
a99dab1d |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove Cyrus_P5020 and P5040 boards These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
3238d934 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove ARCH_P1022 support With the last of the ARCH_P1022 platforms removed, finish removing the rest of the platform support. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2322b956 |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove T2081QDS board and ARCH_T2081 support This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. It is also the only ARCH_T2081 board so remove that support as well. Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
f94cbb5b |
|
25-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio' Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2cc6071e |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8569MDS board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db148f2a |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c00d0012 |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fbe44dd1 |
|
05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com> |
#
08a37fd1 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cdb72c52 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
26bc57da |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
652a7bbd |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0f3d80e9 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5449c98a |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d737010 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
b41f192b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros. |
#
3006ebc3 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4593637b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4167a67d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a990799d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
41c7b7b1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
46d9fc0b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
2f8b8126 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
83b9bea1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9bb1d6bc |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
feb9e25b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7d5f9f84 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
c8f48474 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
23b36a7d |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d07c3843 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3c3d8ab5 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3aff3082 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7f825218 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24ad75ae |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4fd64746 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
115d60c0 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com> |
#
281ed4c7 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> |
#
15a6d496 |
|
17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f3dbf1f0 |
|
01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com> |
#
07d31f8f |
|
25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec2c81c5 |
|
25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
f698e9f3 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8225b2fd |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
a2e225e6 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5818643b |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cc19c25e |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7cad2e38 |
|
29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b9eebfad |
|
15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
48ef0d2a |
|
09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e55782ec |
|
27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
377ffcfa |
|
05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b6808cd8 |
|
28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com> |
#
5122dfae |
|
25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0c12a159 |
|
15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5aef4c86 |
|
26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c3678b09 |
|
28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com> |
#
2a44efeb |
|
21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
bf4699db |
|
30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7af9a074 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb07c0a1 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5b7672fc |
|
27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com> |
#
b135991a |
|
17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> |
#
629d6b32 |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
82a55c1e |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0b66513b |
|
22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com> |
#
9a17eb5b |
|
18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com> |
#
5614e71b |
|
30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com> |
#
8f9fe660 |
|
23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> |
#
2967af68 |
|
17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com> |
#
77354e9d |
|
12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
133fbfa9 |
|
16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com> |
#
ce746fe0 |
|
02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
9dee205d |
|
05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
3b75e982 |
|
04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
6fbe9889 |
|
02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com> |
#
f9d379a7 |
|
01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
b3831020 |
|
25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
69fdf900 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5870fe44 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
8bd00c94 |
|
20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f6981439 |
|
25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5f208d11 |
|
25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b6240846 |
|
25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1e501f91 |
|
25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
45c18853 |
|
25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99d7b0a4 |
|
11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
ada961e2 |
|
24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5e95e2d8 |
|
23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
35fe948e |
|
23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e1dbdd81 |
|
23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b25f6de7 |
|
01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d607b968 |
|
01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e76cd5d4 |
|
23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> |
#
d2404141 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9e758758 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f311838d |
|
08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d1001e3f |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
fd3cebd0 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
92230d49 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f8f85b04 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9a653a98 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f77329cf |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
6d2b9da1 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
4905443f |
|
05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e389a377 |
|
05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
a4c66509 |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
50d96e95 |
|
17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1ca8690d |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
3e978f5d |
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14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
055ce080 |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99abf7de |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
be7bebea |
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10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
81fa73ba |
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08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
19a8dbdc |
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24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
5ffa88ec |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> |
#
7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> |
#
9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6b3a8d00 |
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10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fe1a1da0 |
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04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
c916d7c9 |
|
13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f110fe94 |
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20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f68d3063 |
|
14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
86221f09 |
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12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
e02aea61 |
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08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
df8af0b4 |
|
31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
2bad42a0 |
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09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
4b77047c |
|
22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
b93f81a4 |
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03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4aa8405c |
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27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a52d2f81 |
|
11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
24995d82 |
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20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
67a719da |
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03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d789b5f5 |
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20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
28747f9b |
|
20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d2a9568c |
|
09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17028be2 |
|
17-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
868da593 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1d2c2a62 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
3c6a22b9 |
|
23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ed062e0f |
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17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
680c613a |
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09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a37c36f4 |
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14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ebd7cb0b |
|
02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
9ab87d04 |
|
28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
99d9c07e |
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08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f51cdaf1 |
|
17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
22f292c7 |
|
31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6e37a044 |
|
19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
0c955daf |
|
14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1231c498 |
|
07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17d90f31 |
|
04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ab48ca1a |
|
10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
f94cbb5b |
|
25-Feb-2021 |
Bin Meng <bmeng.cn@gmail.com> |
ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio' Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
2cc6071e |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8569MDS board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db148f2a |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c00d0012 |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fbe44dd1 |
|
05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com> |
#
08a37fd1 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cdb72c52 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
26bc57da |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
652a7bbd |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0f3d80e9 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5449c98a |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d737010 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
b41f192b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros. |
#
3006ebc3 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4593637b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4167a67d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a990799d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
41c7b7b1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
46d9fc0b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
2f8b8126 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
83b9bea1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9bb1d6bc |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
feb9e25b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7d5f9f84 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
c8f48474 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
23b36a7d |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d07c3843 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3c3d8ab5 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3aff3082 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7f825218 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24ad75ae |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4fd64746 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
115d60c0 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com> |
#
281ed4c7 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> |
#
15a6d496 |
|
17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f3dbf1f0 |
|
01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com> |
#
07d31f8f |
|
25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec2c81c5 |
|
25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
f698e9f3 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8225b2fd |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
a2e225e6 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5818643b |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cc19c25e |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7cad2e38 |
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29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b9eebfad |
|
15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
48ef0d2a |
|
09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e55782ec |
|
27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
377ffcfa |
|
05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b6808cd8 |
|
28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com> |
#
5122dfae |
|
25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0c12a159 |
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15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5aef4c86 |
|
26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c3678b09 |
|
28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com> |
#
2a44efeb |
|
21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
bf4699db |
|
30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7af9a074 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb07c0a1 |
|
26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5b7672fc |
|
27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com> |
#
b135991a |
|
17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> |
#
629d6b32 |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
82a55c1e |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0b66513b |
|
22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com> |
#
9a17eb5b |
|
18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com> |
#
5614e71b |
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30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com> |
#
8f9fe660 |
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23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> |
#
2967af68 |
|
17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com> |
#
77354e9d |
|
12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
133fbfa9 |
|
16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com> |
#
ce746fe0 |
|
02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
9dee205d |
|
05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
3b75e982 |
|
04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
6fbe9889 |
|
02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com> |
#
f9d379a7 |
|
01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
b3831020 |
|
25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
69fdf900 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5870fe44 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
8bd00c94 |
|
20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f6981439 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5f208d11 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b6240846 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1e501f91 |
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25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
45c18853 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99d7b0a4 |
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11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
ada961e2 |
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24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5e95e2d8 |
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23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
35fe948e |
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23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e1dbdd81 |
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23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b25f6de7 |
|
01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d607b968 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e76cd5d4 |
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23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> |
#
d2404141 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9e758758 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f311838d |
|
08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d1001e3f |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
fd3cebd0 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
92230d49 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f8f85b04 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9a653a98 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f77329cf |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
6d2b9da1 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
4905443f |
|
05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e389a377 |
|
05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
a4c66509 |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
50d96e95 |
|
17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1ca8690d |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
3e978f5d |
|
14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
055ce080 |
|
14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99abf7de |
|
14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
be7bebea |
|
10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
81fa73ba |
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08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
19a8dbdc |
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24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
5ffa88ec |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> |
#
7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> |
#
9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6b3a8d00 |
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10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
fe1a1da0 |
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04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
c916d7c9 |
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13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f110fe94 |
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20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f68d3063 |
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14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
86221f09 |
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12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
e02aea61 |
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08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
df8af0b4 |
|
31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
2bad42a0 |
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09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
4b77047c |
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22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
b93f81a4 |
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03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
4aa8405c |
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27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a52d2f81 |
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11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
24995d82 |
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20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
67a719da |
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03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d789b5f5 |
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20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
28747f9b |
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20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
d2a9568c |
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09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17028be2 |
|
17-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
868da593 |
|
13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1d2c2a62 |
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13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
3c6a22b9 |
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23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ed062e0f |
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17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
680c613a |
|
09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a37c36f4 |
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14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ebd7cb0b |
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02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
9ab87d04 |
|
28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
99d9c07e |
|
08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f51cdaf1 |
|
17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
22f292c7 |
|
31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
6e37a044 |
|
19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
0c955daf |
|
14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
1231c498 |
|
07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
17d90f31 |
|
04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
ab48ca1a |
|
10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
a47a12be |
|
15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
#
2cc6071e |
|
20-Feb-2021 |
Tom Rini <trini@konsulko.com> |
ppc: Remove MPC8569MDS board This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. As this is the last ARCH_MPC8569 board, remove that support as well. Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
#
db148f2a |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
c00d0012 |
|
08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
44262327 |
|
15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
fbe44dd1 |
|
05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com> |
#
08a37fd1 |
|
28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cdb72c52 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
26bc57da |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
652a7bbd |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
0f3d80e9 |
|
21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5449c98a |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5d737010 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e5d5f5a8 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5ff3f41d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
b41f192b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros. |
#
3006ebc3 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
95390360 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
cefe11cd |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
e71372cb |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
5e5fdd2d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
ce040c83 |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4593637b |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4167a67d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
a990799d |
|
18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
41c7b7b1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
46d9fc0b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
2f8b8126 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
83b9bea1 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com> |
#
9bb1d6bc |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
feb9e25b |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7d5f9f84 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
c8f48474 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
23b36a7d |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
d07c3843 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3c3d8ab5 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
3aff3082 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
7f825218 |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
24ad75ae |
|
16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
4fd64746 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com> |
#
115d60c0 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com> |
#
281ed4c7 |
|
15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com> |
#
15a6d496 |
|
17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
f3dbf1f0 |
|
01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com> |
#
07d31f8f |
|
25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com> |
#
ec2c81c5 |
|
25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
f698e9f3 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
0a6b2714 |
|
22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
#
8225b2fd |
|
26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e04916a7 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
a2e225e6 |
|
26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5818643b |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
cc19c25e |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
f6050790 |
|
24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7cad2e38 |
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29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b9eebfad |
|
15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
48ef0d2a |
|
09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
e55782ec |
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27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
377ffcfa |
|
05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
b6808cd8 |
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28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com> |
#
5122dfae |
|
25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0c12a159 |
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15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5aef4c86 |
|
26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
c3678b09 |
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28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com> |
#
2a44efeb |
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21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
bf4699db |
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30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
7af9a074 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
fb07c0a1 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
#
5b7672fc |
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27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com> |
#
b135991a |
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17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> |
#
629d6b32 |
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22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
82a55c1e |
|
22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> |
#
0b66513b |
|
22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com> |
#
9a17eb5b |
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18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com> |
#
5614e71b |
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30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com> |
#
8f9fe660 |
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23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> |
#
2967af68 |
|
17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com> |
#
77354e9d |
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12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
#
133fbfa9 |
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16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com> |
#
ce746fe0 |
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02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
#
9dee205d |
|
05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
3b75e982 |
|
04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com> |
#
6fbe9889 |
|
02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com> |
#
f9d379a7 |
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01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
b3831020 |
|
25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com> |
#
1a459660 |
|
08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> |
#
69fdf900 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5870fe44 |
|
07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
8bd00c94 |
|
20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f6981439 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5f208d11 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b6240846 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1e501f91 |
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25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
45c18853 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99d7b0a4 |
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11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
ada961e2 |
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24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
5e95e2d8 |
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23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
35fe948e |
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23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e1dbdd81 |
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23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
b25f6de7 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d607b968 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e76cd5d4 |
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23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> |
#
d2404141 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9e758758 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f311838d |
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08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
d1001e3f |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
fd3cebd0 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
92230d49 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f8f85b04 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
9a653a98 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
f77329cf |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
6d2b9da1 |
|
08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
4905443f |
|
05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
e389a377 |
|
05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
a4c66509 |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
50d96e95 |
|
17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
1ca8690d |
|
17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
3e978f5d |
|
14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
055ce080 |
|
14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
99abf7de |
|
14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
be7bebea |
|
10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
81fa73ba |
|
08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
#
19a8dbdc |
|
24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
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5ffa88ec |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> |
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7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> |
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9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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6b3a8d00 |
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10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@nxp.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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fe1a1da0 |
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04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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c916d7c9 |
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13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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f110fe94 |
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20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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f68d3063 |
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14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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86221f09 |
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12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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e02aea61 |
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08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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df8af0b4 |
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31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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2bad42a0 |
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09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> |
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4b77047c |
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22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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b93f81a4 |
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03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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4aa8405c |
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27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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a52d2f81 |
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11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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24995d82 |
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20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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67a719da |
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03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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d789b5f5 |
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20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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28747f9b |
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20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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d2a9568c |
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09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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17028be2 |
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17-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> |
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868da593 |
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13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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1d2c2a62 |
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13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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3c6a22b9 |
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23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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ed062e0f |
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17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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680c613a |
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09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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a37c36f4 |
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14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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ebd7cb0b |
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02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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9ab87d04 |
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28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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99d9c07e |
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08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
#
f51cdaf1 |
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17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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22f292c7 |
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31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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6e37a044 |
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19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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0c955daf |
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14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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1231c498 |
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07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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17d90f31 |
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04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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ab48ca1a |
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10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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a47a12be |
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15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de> |
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db148f2a |
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08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW EC2 settings Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2 settings. - The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should be 0x04000000 (value of 1 in RCW bit [420:421]) - Value of 2/3 are reserved in RCW bit [420:421], hence there is no macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
c00d0012 |
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08-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
powerpc: t1040: Correct RCW MAC2_GMII_SEL value Per T1040RM (Rev. 1, 08/2015), the value of FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT is wrong and should be 0x00000080 (bit 440 in the RCW). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
44262327 |
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15-Dec-2017 |
Ahmed Mansour <ahmed.mansour@nxp.com> |
drivers/misc: Share qbman init between archs This patch adds changes necessary to move functionality present in PowerPC folders with ARM architectures that have DPAA1 QBMan hardware - Create new board/freescale/common/fsl_portals.c to house shared device tree fixups for DPAA1 devices with ARM and PowerPC cores - Add new header file to top includes directory to allow files in both architectures to grab the function prototypes - Port inhibit_portals() from PowerPC to ARM. This function is used in setup to disable interrupts on all QMan and BMan portals. It is needed because the interrupts are enabled by default for all portals including unused/uninitialised portals. When the kernel attempts to go to deep sleep the unused portals prevent it from doing so Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
fbe44dd1 |
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05-May-2017 |
Paulo Zaneti <paulo.zaneti@datacom.ind.br> |
powerpc: t1024: Fix SRDS_MAX_LANES value T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com>
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#
08a37fd1 |
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28-Dec-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc85xx: Remove variant SoCs T1020/T1022/T1013/T1014 Remove these SoCs from Kconfig because they don't have individual configuration. Clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
cdb72c52 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4080: Drop configuration for T4080 There is no T4080 target. Drop related macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
26bc57da |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4240: Remove macro CONFIG_PPC_T4240 Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
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#
652a7bbd |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T4160: Remove macro CONFIG_PPC_T4160 Use CONFIG_ARCH_T4160 instead. Signed-off-by: York Sun <york.sun@nxp.com>
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#
0f3d80e9 |
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21-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T2080, T2081: Remove macro CONFIG_PPC_T2080 and CONFIG_PPC_T2081 Use CONFIG_ARCH_T2080 and CONFIG_ARCH_T2081 instead. Signed-off-by: York Sun <york.sun@nxp.com>
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#
5449c98a |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1042: Remove macro CONFIG_PPC_T1042 Replace CONFIG_PPC_T1042 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
5d737010 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1040: Remove macro CONFIG_PPC_T1040 Replace CONFIG_PPC_T1040 with ARCH_T1040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
e5d5f5a8 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1024: Remove macro CONFIG_PPC_T1024 Replace CONFIG_PPC_T1024 with ARCH_T1024 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
5ff3f41d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: T1023: Remove macro CONFIG_PPC_T1023 Replace CONFIG_PPC_T1023 with ARCH_T1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
b41f192b |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4420: Remove macro CONFIG_PPC_B4420 Replace CONFIG_PPC_B4420 with ARCH_B4420 in Kconfig and clean up existing macros.
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#
3006ebc3 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: B4860: Remove macro CONFIG_PPC_B4860 Replace CONFIG_PPC_B4860 with ARCH_B4860 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
95390360 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5040: Remove macro CONFIG_P5040 Replace CONFIG_P5040 with ARCH_P5040 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
cefe11cd |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P5020: Remove macro CONFIG_PPC_P5020 Replace CONFIG_PPC_P5020 with ARCH_P5020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
e71372cb |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P4080: Remove macro CONFIG_PPC_P4080 Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
5e5fdd2d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P3041: Remove macro CONFIG_PPC_P3041 Replace CONFIG_PPC_P3041 with ARCH_P3041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
ce040c83 |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2041: Remove macro CONFIG_PPC_P2041 Replace CONFIG_PPC_P2041 with ARCH_P2041 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
4593637b |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P2020: Remove macro CONFIG_P2020 Replace CONFIG_P2020 with ARCH_P2020 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
4167a67d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1025: Remove macro CONFIG_P1025 Replace CONFIG_P1025 with ARCH_P1025 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
a990799d |
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18-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1021: Remove macro CONFIG_P1021 Replace CONFIG_P1021 with ARCH_P1021 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
41c7b7b1 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1017: Drop configuration for P1017 P1017 is a single-core version of P1023. There is no P1017 target configured. Drop related macros. P1017 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
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#
46d9fc0b |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1014: Drop configuration for P1014 P1014 is a variant of P1010. There is no P1014 target configured. Drop related macros. P1014 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
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#
2f8b8126 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1013: Drop configuration for P1013 P1013 is a single-core version of P1022. There is no P1022 target configured. Drop related macros. P1022 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
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#
83b9bea1 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1012: Drop configuration for P1012 P1012 is a single-core version of P1021. There is no P1012 target configured. Drop related macros. P1012 SoC is still supported. Signed-off-by: York Sun <york.sun@nxp.com>
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#
9bb1d6bc |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1023: Remove macro CONFIG_P1023 Replace CONFIG_P1023 with ARCH_P1023 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
feb9e25b |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1022: Remove macro CONFIG_P1022 Replace CONFIG_P1022 with ARCH_P1022 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
7d5f9f84 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: P1010: Remove macro CONFIG_P1010 Replace CONFIG_P1010 with ARCH_P1010 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
c8f48474 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8572: Remove macro CONFIG_MPC8572 Replace CONFIG_MPC8572 with ARCH_MPC8572 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
23b36a7d |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8569: Remove macro CONFIG_MPC8569 Replace CONFIG_MPC8569 with ARCH_MPC8569 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
d07c3843 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8568: Remove macro CONFIG_MPC8568 Replace CONFIG_MPC8568 with ARCH_MPC8568 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
3c3d8ab5 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8555: Remove macro CONFIG_MPC8555 Replace CONFIG_MPC8555 with ARCH_MPC8555 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
3aff3082 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8541: Remove macro CONFIG_MPC8541 Replace CONFIG_MPC8541 with ARCH_MPC8541 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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7f825218 |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: mpc8540: Remove macro CONFIG_MPC8540 Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
24ad75ae |
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16-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8536: Move CONFIG_MPC8536 to Kconfig option Replace CONFIG_MPC8536 with ARCH_MPC8536 in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
4fd64746 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: C29X: Move CONFIG_PPC_C29X to Kconfig option Replace CONFIG_PPC_C29X with ARCH_C29X in Kconfig and clean up existing macros. Signed-off-by: York Sun <york.sun@nxp.com>
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#
115d60c0 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: BSC9131/2: Move CONFIG_BSC9131/2 to Kconfig options Replace CONFIG_BSC9131, CONFIG_BSC9132 with ARCH_BSC9131, ARCH_BSC9132 Kconfig options. Also drop #ifdef in BSC9131RDB.h since it is redundant. Signed-off-by: York Sun <york.sun@nxp.com>
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281ed4c7 |
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15-Nov-2016 |
York Sun <york.sun@nxp.com> |
powerpc: MPC8548: Move CONFIG_MPC8548 to Kconfig option Replace CONFIG_MPC8548 with ARCH_MPC8548 in Kconfig. Signed-off-by: York Sun <york.sun@nxp.com>
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15a6d496 |
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17-Aug-2016 |
Sriram Dash <sriram.dash@nxp.com> |
mpc85xx: powerpc: usb: Enable Usb phy initialisation settings for P1010 CONFIG_SYS_FSL_USB1_PHY_ENABLE is set and the USB Phy offset are set to enable the initial setting of Usb Phy for P1010. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
f3dbf1f0 |
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01-Aug-2016 |
York Sun <york.sun@nxp.com> |
powerpc/mpc85xx: Update erratum workaround for A006379 Update erratum workaround for A006379 to set register CPCHDBCR0 with value 0x001e0000, replacing the old value 0x003c0000. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Dave Liu <dave.liu@nxp.com>
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07d31f8f |
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25-May-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: gpio: Add driver for MPC85XX GPIO controller This patch adds a driver for the built-in GPIO controller of the MPC85XX SoC (probably supporting other PowerQUICC III SoCs as well). Each GPIO bank is identified by its own entry in the device tree, i.e. gpio-controller@fc00 { #gpio-cells = <2>; compatible = "fsl,pq3-gpio"; reg = <0xfc00 0x100> } By default, each bank is assumed to have 32 GPIOs, but the ngpios setting is honored, so the number of GPIOs for each bank in configurable to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of the P1022 SoC). The usual functions of GPIO drivers (setting input/output mode and output value setting) are supported. The driver has been tested on MPC85XX, but it is likely that other PowerQUICC III devices will work as well. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
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#
ec2c81c5 |
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25-Apr-2016 |
mario.six@gdsys.cc <mario.six@gdsys.cc> |
dm: fsl_i2c: Rename I2C register structure Signed-off-by: Mario Six <mario.six@gdsys.cc>
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#
f698e9f3 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
powerpc/SECURE_BOOT: Add PAMU driver PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
0a6b2714 |
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22-Jan-2016 |
Aneesh Bansal <aneesh.bansal@nxp.com> |
secure_boot: create function to determine boot mode A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
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#
8225b2fd |
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26-Oct-2015 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
net: Move some header files to include/ The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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#
e04916a7 |
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26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms. esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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#
a2e225e6 |
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26-Feb-2015 |
gaurav rana <gaurav.rana@freescale.com> |
fsl_sfp : Move ccsr_sfp_regs definition to common include Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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#
5818643b |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
t1024qds: increase IO drive strength Increase IO drive strength to fix FCS error on RGMII ports on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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#
cc19c25e |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: update 10GEC to fit new SoC fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER. but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs. on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below: 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below: 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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f6050790 |
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24-Nov-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T1024/T1023 SoC support Add support for Freescale T1024/T1023 SoC. The T1024 SoC includes the following function and features: - Two 64-bit Power architecture e5500 cores, up to 1.4GHz - private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC) - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration - Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI) - High-speed peripheral interfaces - Three PCI Express 2.0 controllers - Additional peripheral interfaces - One SATA 2.0 controller - Two USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/eSDHC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Two 8-channel DMA engines - Multicore programmable interrupt controller (PIC) - LCD interface (DIU) with 12 bit dual data rate - QUICC Engine block supporting TDM, HDLC, and UART - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB) - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T1024 and T1023: Feature T1024 T1023 QUICC Engine: yes no DIU: yes no Deep Sleep: yes no I2C controller: 4 3 DDR: 64-bit 32-bit IFC: 32-bit 28-bit Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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7cad2e38 |
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29-Sep-2014 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot By default, PAMU's (IOMMU) are enabled in case of secure boot. Disable/bypass them once the control reaches the bootloader. For non-secure boot, PAMU's are already bypassed in the default SoC configuration. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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b9eebfad |
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15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
fsl_sec: Add hardware accelerated SHA256 and SHA1 SHA-256 and SHA-1 accelerated using SEC hardware in Freescale SoC's The driver for SEC (CAAM) IP is based on linux drivers/crypto/caam. The platforms needto add the MACRO CONFIG_FSL_CAAM inorder to enable initialization of this hardware IP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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48ef0d2a |
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09-Sep-2014 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
fsl_sec : Move SEC CCSR definition to common include Freescale SEC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of SEC to common include Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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e55782ec |
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27-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/t4240qds: fix offset of serdes when checking reference clock T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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377ffcfa |
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05-Jun-2014 |
Sandeep Singh <sandeep@freescale.com> |
powerpc/mpc85xx: Add workaround to enable TDM on T1040 This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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b6808cd8 |
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28-May-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/serdes: Add the workaround for erratum A-007186 SerDes PLL is calibrated at reset. When the junction temperature delta from the time the PLL is calibrated exceeds +56C/-66C, jitter may increase and can cause PLL to unlock. This workaround overwrite the SerDes registers with new values, to calibrate SerDes registers. These values are known to work fine for all temperature ranges. This workaround is valid for B4, T4 and T2 platforms, so added in their config. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> [York Sun: replaced typedef ccsr_sfp_regs_t with struct ccsr_sfp_regs] Reviewed-by: York Sun <yorksun@freescale.com>
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5122dfae |
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25-Apr-2014 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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0c12a159 |
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15-Apr-2014 |
vijay rai <vijay.rai@freescale.com> |
powerpc/85xx: Enhance get_sys_info() to check clocking mode T1040 and it's variants provide "Single Oscillator Source" Reference Clock Mode. In this mode, single onboard oscillator(DIFF_SYSCLK) can provide the reference clock (100MHz) to the following PLLs: • Platform PLL • Core PLLs • USB PLL • DDR PLL, etc The cfg_eng_use0 of porsr1 register identifies whether the SYSCLK (single-ended) or DIFF_SYSCLK (differential) is selected as the clock input to the chip. get_sys_info has been enhanced to add the diff_sysclk so that the various drivers can be made aware of ths diff sysclk configuration and act accordingly. Other changes: -single_src to ddr_refclk_sel, as it is use for checking ddr reference clock -Removed the print of single_src from get_sys_info as this will be -printed whenever somebody calls get_sys_info which is not appropriate. -Add print of single_src in checkcpu as it is called only once during initialization Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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5aef4c86 |
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26-Mar-2014 |
Tang Yuantian <yuantian.tang@freescale.com> |
mpc85xx: Add support for the supplement configuration unit register The supplement configuration unit (SCFG) provides chip-specific configuration and status registers for the device. It is the chip defined module for extending the device configuration unit (DCFG) module. It provides a set of CCSR registers in addition to those available in the device configuration unit. The base address for this unit is 0x0F_C000. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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c3678b09 |
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28-Mar-2014 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A007212 Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: York Sun <yorksun@freescale.com>
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2a44efeb |
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21-Mar-2014 |
Zhao Qiang <B45475@freescale.com> |
QE/U-QE: Add U-QE support Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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bf4699db |
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30-Jan-2014 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add SCFG_PIXCLKCR register support for T1040 T1040 SoC has SCFG (Supplement Configuration) Block which provides chip specific configuration and status support. The base address of SCFG block in T1040 is 0xfc000. SCFG contains SCFG_PIXCLKCR (DIU pixel clock control register) at offset 0x28. Add definition of -SCFG block -SCFG_PIXCLKCR register -Bits definition of SCFG_PIXCLK register Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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7af9a074 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/b4860: Add workaround for errata A006384 and A006475 SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384) and at cold temperatures(A006475), workaround recalibrate the PLLs with some SerDes configuration Both these errata are only applicable for b4 rev1. So, make workaround for these errata conditional, depending upon soc version. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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fb07c0a1 |
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26-Feb-2014 |
Shaveta Leekha <shaveta@freescale.com> |
board/b4860qds: Add support to make PCIe SATA work on B4860QDS 1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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5b7672fc |
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27-Jan-2014 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel <B44344@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: remove dash from commit message] Signed-off-by: York Sun <yorksun@freescale.com>
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b135991a |
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17-Dec-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/mpc85xx: Add support for single source clocking Single-source clocking is new feature introduced in T1040. In this mode, a single differential clock is supplied to the DIFF_SYSCLK_P/N inputs to the processor, which in turn is used to supply clocks to the sysclock, ddrclock and usbclock. So, both ddrclock and syclock are driven by same differential sysclock in single-source clocking mode whereas in normal clocking mode, generally separate DDRCLK and SYSCLK pins provides reference clock for sysclock and ddrclock DDR_REFCLK_SEL rcw bit is used to determine DDR clock source -If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in normal clocking mode by DDR_Reference clock -If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in single source clocking mode by DIFF_SYSCLK Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
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629d6b32 |
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22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/mpc85xx: Add T2080/T2081 SoC support Add support for Freescale T2080/T2081 SoC. T2080 includes the following functions and features: - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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82a55c1e |
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22-Nov-2013 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
net/fman: Add support for 10GEC3 and 10GEC4 There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080). This patch adds support for 10GEC3 and 10GEC4. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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0b66513b |
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22-Oct-2013 |
York Sun <yorksun@freescale.com> |
Driver/IFC: Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/misc and fix the header file includes. Signed-off-by: York Sun <yorksun@freescale.com>
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9a17eb5b |
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18-Nov-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3 structure for 83xx, 85xx and 86xx. Signed-off-by: York Sun <yorksun@freescale.com>
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5614e71b |
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30-Sep-2013 |
York Sun <yorksun@freescale.com> |
Driver/DDR: Moving Freescale DDR driver to a common driver Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
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8f9fe660 |
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23-Oct-2013 |
Laurentiu TUDOR <Laurentiu.Tudor@freescale.com> |
powerpc/t4240: fix per pci endpoint liodn offsets Update the code that builds the pci endpoint liodn offset list so that it doesn't overlap with other liodns and doesn't generate negative offsets like: fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf 0xffffffd1 0xffffffd3 0xffffffd5 0xffffffd7 0xffffffd9 0xffffffdb>; The update consists in adding a parameter to the function that builds the list to specify the base liodn. On PCI v2.4 use the old base = 256 and, on PCI 3.0 where some of the PCIE liodns are larger than 256, use a base = 1024. The version check is based on the PCI controller's version register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com>
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2967af68 |
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17-Oct-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
powerpc/t1040: Update defines to support T1040SoC personalities T1040 Soc has four personalities: -T1040 (4 cores with L2 switch) -T1042:Reduced personality of T1040 without L2 switch -T1020:Reduced personality of T1040 with less cores(2 cores) -T1022:Reduced personality of T1040 with 2 cores and without L2 switch Update defines in arch/powerpc header files, Makefiles and in driver/net/fm/Makefile to support all T1040 personalities Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> [York Sun: fixed Makefiles] Acked-by: York Sun <yorksun@freescale.com>
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77354e9d |
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12-Sep-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
powerpc/usb:Differentiate USB controller base address Introduce different macros for storing addresses of multiple USB controllers. This is required for successful initialization and usage of multiple USB controllers inside u-boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
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133fbfa9 |
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16-Sep-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add workaround for erratum A006379 Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
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ce746fe0 |
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02-Sep-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW accelerator CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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9dee205d |
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05-Aug-2013 |
ramneek mehresh <ramneek.mehresh@freescale.com> |
fsl/usb: Move USB internal phy definitions to fsl_usb.h fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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3b75e982 |
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04-Jul-2013 |
Mingkai Hu <Mingkai.Hu@freescale.com> |
powerpc/85xx: Add C29x SoC support The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
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6fbe9889 |
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02-Jul-2013 |
Shaveta Leekha <shaveta@freescale.com> |
powerpc/mpc85xx: Add defines for serdes RSTCTL register Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
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f9d379a7 |
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01-Jul-2013 |
Priyanka Jain <Priyanka.Jain@freescale.com> |
board/bsc9132qds: Configure DSP DDR controller BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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b3831020 |
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25-Jun-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Update the SRIO LIODN registers and ID table macro For some PowerPC platforms, LIODN registers for SRIO ports are in SRIO register address space. So the ccsr_rio structure should be updated for those LIODN registers. In addition, add a new macro "SET_SRIO_LIODN_BASE" to create the SRIO LIODN ID table based on the SRIO LIODN register address. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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1a459660 |
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08-Jul-2013 |
Wolfgang Denk <wd@denx.de> |
Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
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69fdf900 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/t4qds: Slave module for boot from SRIO and PCIE When a T4 board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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5870fe44 |
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07-May-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4860qds: Slave module for boot from SRIO and PCIE When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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8bd00c94 |
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20-Jun-2013 |
Andy Fleming <afleming@freescale.com> |
85xx: Change case of MPC85XX_PORBMSR_ROMLOC_SHIFT All the other constants use lowercase 'x' in "MPC85xx", so we duplicate that here. Signed-off-by: Andy Fleming <afleming@freescale.com>
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f6981439 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/chassis2: Change core numbering scheme To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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5f208d11 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add T1040 and variant SoCs T1040 and variants have e5500 cores and are compliant to QorIQ Chassis Generation 2. The major difference between T1040 and its variants is the number of cores and the number of L2 switch ports. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
b6240846 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4160 SoC T4160 SoC is low power version of T4240. The T4160 combines eight dual threaded Power Architecture e6500 cores and two memory complexes (CoreNet platform cache and DDR3 memory controller) with the same high-performance datapath acceleration, networking, and peripheral bus interfaces. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
1e501f91 |
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25-Mar-2013 |
Roy Zang <tie-fei.zang@freescale.com> |
T4/USB: Add USB 2.0 UTMI dual phy support T4240 internal UTMI phy is different comparing to previous UTMI PHY in P3041. This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for T4240. The phy timing is very sensitive and moving the phy enable code to cpu_init.c will not work. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
45c18853 |
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25-Mar-2013 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Update corenet global utility block registers Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse status register. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
99d7b0a4 |
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11-Mar-2013 |
Xulei <B33228@freescale.com> |
powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0) On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
ada961e2 |
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24-Feb-2013 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/b4: Fix the wrong register offset of B4 PCIE module B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
5e95e2d8 |
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23-Jan-2013 |
Vakul Garg <vakul@freescale.com> |
powerpc/mpc85xx: Add property 'fsl, sec-era' in device tree node 'crypto' If property 'fsl,sec-era' is already present, it is updated. This property is required so that applications can ascertain which descriptor commands are supported on a particular CAAM version. Signed-off-by: Vakul Garg <vakul@freescale.com> Cc: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
35fe948e |
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23-Jan-2013 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx: Add BSC9132/BSC9232 processor support The BSC9132 is a highly integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 core technologies with MAPLE-B2P baseband acceleration processing elements to address the need for a high performance, low cost, integrated solution that handles all required processing layers without the need for an external device except for an RF transceiver or, in a Micro base station configuration, a host device that handles the L3/L4 and handover between sectors. The BSC9132 SoC includes the following function and features: - Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache - 32 Kbyte of shared M3 memory - The Multi Accelerator Platform Engine for Pico BaseStation Baseband Processing (MAPLE-B2P) - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate - Dedicated security engine featuring trusted boot - Two DMA controllers - OCNDMA with four bidirectional channels - SysDMA with sixteen bidirectional channels - Interfaces - Four-lane SerDes PHY - PCI Express controller complies with the PEX Specification-Rev 2.0 - Two Common Public Radio Interface (CPRI) controller lanes - High-speed USB 2.0 host and device controller with ULPI interface - Enhanced secure digital (SD/MMC) host controller (eSDHC) - Antenna interface controller (AIC), supporting four industry standard JESD207/four custom ADI RF interfaces - ADI lanes support both full duplex FDD support & half duplex TDD - Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards - Two DUART, two eSPI, and two I2C controllers - Integrated Flash memory controller (IFC) - GPIO - Sixteen 32-bit timers Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
e1dbdd81 |
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23-Dec-2012 |
Poonam Aggrwal <poonam.aggrwal@freescale.com> |
powerpc/mpc85xx:Add support of B4420 SoC B4420 is a reduced personality of B4860 with fewer core/clusters(both SC3900 and e6500), fewer DDR controllers, fewer serdes lanes, fewer SGMII interfaces and reduced target frequencies. Key differences between B4860 and B4420 ---------------------------------------- B4420 has: 1. Fewer e6500 cores: 1 cluster with 2 e6500 cores 2. Fewer SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. 3. Single DDRC 4. 2X 4 lane serdes 5. 3 SGMII interfaces 6. no sRIO 7. no 10G Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
b25f6de7 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: update the work-around for P4080 erratum SERDES-9 The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
d607b968 |
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01-Nov-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: implement check for erratum A-004580 work-around The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
e76cd5d4 |
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23-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
8xxx: Change all 8*xx_DDR addresses to 8xxx There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: Andy Fleming <afleming@freescale.com> Tested-by: Andy Fleming <afleming@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
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#
d2404141 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
9e758758 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add T4240 SoC Add support for Freescale T4240 SoC. Feature of T4240 are (incomplete list): 12 dual-threaded e6500 cores built on Power Architecture® technology Arranged as clusters of four cores sharing a 2 MB L2 cache. Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture v2.06-compliant) Three levels of instruction: user, supervisor, and hypervisor 1.5 MB CoreNet Platform Cache (CPC) Hierarchical interconnect fabric CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet end-points 1.6 Tbps coherent read bandwidth Queue Manager (QMan) fabric supporting packet-level queue management and quality of service scheduling Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Memory prefetch engine (PMan) Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Packet parsing, classification, and distribution (Frame Manager 1.1) Queue management for scheduling, packet sequencing, and congestion management (Queue Manager 1.1) Hardware buffer management for buffer allocation and de-allocation (BMan 1.1) Cryptography acceleration (SEC 5.0) at up to 40 Gbps RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0) 32 SerDes lanes at up to 10.3125 GHz Ethernet interfaces Up to four 10 Gbps Ethernet MACs Up to sixteen 1 Gbps Ethernet MACs Maximum configuration of 4 x 10 GE + 8 x 1 GE High-speed peripheral interfaces Four PCI Express 2.0/3.0 controllers Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with Type 11 messaging and Type 9 data streaming support Interlaken look-aside interface for serial TCAM connection Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Four I2C controllers Four 2-pin or two 4-pin UARTs Integrated Flash controller supporting NAND and NOR flash Two eight-channel DMA engines Support for hardware virtualization and partitioning enforcement QorIQ Platform's Trust Architecture 1.1 Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
f311838d |
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08-Oct-2012 |
Andy Fleming <afleming@freescale.com> |
powerpc/mpc85xx: Add T4 device definitions The T4 has added devices to previous corenet implementations: * SEC has 3 more DECO units * New PMAN device * New DCE device This doesn't add full support for the new devices. Just some preliminary support. Move PMAN LIODN to upper half of register Despite having only one LIODN, the PMAN LIODN is stored in the upper half of the register. Re-use the 2-LIODN code and just set the LIODN as if the second one is 0. This results in the actual LIODN being written to the upper half of the register. Signed-off-by: Andy Fleming <afleming@freescale.com>
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d1001e3f |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/corenet2: Add SerDes for corenet2 Create new files to handle 2nd generation Chassis as the registers are organized differently. - Add SerDes protocol parsing and detection - Add support of 4 SerDes - Add CPRI protocol in fsl_serdes.h The Common Public Radio Interface (CPRI) is publicly available specification that standardizes the protocol interface between the radio equipment control (REC) and the radio equipment (RE) in wireless basestations. This allows interoperability of equipment from different vendors,and preserves the software investment made by wireless service providers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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fd3cebd0 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Add RCW bits and registers for SerDes for corenet2 Corenet 2nd generation Chassis has different RCW and registers for SerDes. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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92230d49 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/e6500: Move QCSP registers for QMan v3 The QCSP registers are expanded and moved from offset 0 to offset 0x1000 for SoCs with QMan v3. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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f8f85b04 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: expand SERDES reference clock select bit Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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#
9a653a98 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Fix core cluster PLL calculation for Chassis generation 2 Corenet based SoCs have different core clocks starting from Chassis generation 2. Cores are organized into clusters. Each cluster has up to 4 cores sharing same clock, which can be chosen from one of three PLLs in the cluster group with one of the devisors /1, /2 or /4. Two clusters are put together as a cluster group. These two clusters share the PLLs but may have different divisor. For example, core 0~3 are in cluster 1. Core 4~7 are in cluster 2. Core 8~11 are in cluster 3 and so on. Cluster 1 and 2 are cluster group A. Cluster 3 and 4 are in cluster group B. Cluster group A has PLL1, PLL2, PLL3. Cluster group B has PLL4, PLL5. Core 0~3 may have PLL1/2, core 4~7 may have PLL2/2. Core 8~11 may have PLL4/1. PME and FMan blocks can take different PLLs, configured by RCW. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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f77329cf |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: change RCW MEM_PLL_PLAT for Chassis generation 2 Chassis generation 2 has different mask and shift. Use macro instead of magic numbers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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6d2b9da1 |
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08-Oct-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc85xx: Enable L2 at the beginning of U-boot for E6500 Using E6500 L1 cache as initram requires L2 cache enabled. Add l2-cache cluster enabling. Setup stash id for L1 cache as (coreID) * 2 + 32 + 0 Setup stash id for L2 cache as (cluster) * 2 + 32 + 1 Stash id for L2 is only set for Chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
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4905443f |
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05-Oct-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Add P5040 processor support Add support for the Freescale P5040 SOC, which is similar to the P5020. Features of the P5040 are: Four P5040 single-threaded e5500 cores built Up to 2.4 GHz with 64-bit ISA support Three levels of instruction: user, supervisor, hypervisor CoreNet platform cache (CPC) 2.0 MB configures as dual 1 MB blocks hierarchical interconnect fabric Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support Up to 1600MT/s Memory pre-fetch engine DPAA incorporating acceleration for the following functions Packet parsing, classification, and distribution (FMAN) Queue management for scheduling, packet sequencing and congestion management (QMAN) Hardware buffer management for buffer allocation and de-allocation (BMAN) Cryptography acceleration (SEC 5.2) at up to 40 Gbps SerDes 20 lanes at up to 5 Gbps Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces Two 10 Gbps Ethernet MACs Ten 1 Gbps Ethernet MACs High-speed peripheral interfaces Two PCI Express 2.0/3.0 controllers Additional peripheral interfaces Two serial ATA (SATA 2.0) controllers Two high-speed USB 2.0 controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface (eSPI) Two I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash DMA Dual four channel Support for hardware virtualization and partitioning enforcement Extra privileged level for hypervisor support QorIQ Trust Architecture 1.1 Secure boot, secure debug, tamper detection, volatile key storage Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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e389a377 |
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05-Oct-2012 |
Laurentiu Tudor <Laurentiu.Tudor@freescale.com> |
powerpc/85xx: introduce SET_PCI_LIODN_BASE, for setting PCI LIODNs The liodn for the new PCIE controller included in P5040DS is no longer set through a register in the guts register block but with one in the PCIE register block itself. Update the PCIE CCSR structure to add the new liodn register and add a new dedicated SET_PCI_LIODN_BASE macro that puts the liodn in the correct register. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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a4c66509 |
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17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Enable 3-way and 4-way DDR interleaving Restructure DDR interleaving option to support 3 and 4 DDR controllers for 2-, 3- and 4-way interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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50d96e95 |
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17-Aug-2012 |
Kumar Gala <galak@kernel.crashing.org> |
Add IFC offset for DPAA/Corenet platforms Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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1ca8690d |
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17-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Add immap for topology and rcpm registers Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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3e978f5d |
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14-Aug-2012 |
Scott Wood <scottwood@freescale.com> |
powerpc/fsl-corenet: remove dead variant symbols These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
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055ce080 |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove support for the Freescale P3060 The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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99abf7de |
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14-Aug-2012 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: add support for FM2 DTSEC5 Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second Fman, so add the Fman and SerDes macros for that DTSEC. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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be7bebea |
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10-Aug-2012 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list P1015 is the same as P1011 and P1016 is the same as P1012 from software point of view. They have different packages but share SVRs. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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81fa73ba |
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08-Aug-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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19a8dbdc |
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24-Apr-2012 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support - BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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5ffa88ec |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/corenet_ds: Master module for boot from SRIO For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. For the master module, need to finish these processes: 1. Initialize the SRIO port and address space. 2. Set inbound SRIO windows covered slave's u-boot image stored in master's NOR flash. 3. Master's u-boot image should be generated specifically by make xxxx_SRIOBOOT_MASTER_config 4. Master must boot first, and then slave can be powered on. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
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7d67ed58 |
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07-Mar-2012 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio: Rewrite the struct ccsr_rio Rewrite this struct for the support of two ports and two message units registers. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
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9839709e |
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23-Nov-2011 |
Ira W. Snyder <iws@ovro.caltech.edu> |
mpc85xx: support for Freescale COM Express P2020 This adds support for the Freescale COM Express P2020 board. This board is similar to the P1_P2_RDB, but has some extra (as well as missing) peripherals. Unlike all other mpc85xx boards, it uses a watchdog timeout to reset. Using the HRESET_REQ register does not work. This board has no NOR flash, and can only be booted via SD or SPI. This procedure is documented in Freescale Document Number AN3659 "Booting from On-Chip ROM (eSDHC or eSPI)." Some alternative documentation is provided in Freescale Document Number P2020RM "P2020 QorIQ Integrated Processor Reference Manual" (section 4.5). Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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4d28db8a |
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14-Oct-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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7f92c3a2 |
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13-Oct-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/p3060: remove all references to RCW bits EC1_EXT, EC2_EXT, and EC3 The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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ae2044d8 |
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03-Oct-2011 |
Xie Xiaobo <r63061@freescale.com> |
powerpc/mpc8536ds: Add eSPI support for MPC8536DS 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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6d7b061a |
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31-Aug-2011 |
Shengzhou Liu <Shengzhou.Liu@freescale.com> |
powerpc/p3060: Add SoC related support for P3060 platform Add P3060 SoC specific information:cores setup, LIODN setup, etc The P3060 SoC combines six e500mc Power Architecture processor cores with high-performance datapath acceleration architecture(DPAA), CoreNet fabric infrastructure, as well as network and peripheral interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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6b3a8d00 |
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10-Sep-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for setting up RAID engine liodns on P5020 Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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7065b7d4 |
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15-Dec-2010 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
powerpc/p4080: Add support for secure boot flow Pre u-boot Flow: 1. User loads the u-boot image in flash 2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000 (Please note that ISBC expects all these addresses, images to be validated, entry point etc within 0 - 3.5G range) 3. ISBC validates the u-boot image, and passes control to u-boot at 0xcffffffc. Changes in u-boot: 1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M CONFIG_SYS_PBI_FLASH_WINDOW in AS=1. (The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash created by PBL/configuration word within 0 - 3.5G memory range. The u-boot image at this address has been validated by ISBC code) 2. Remove TLB entries for 0 - 3.5G created by ISBC code 3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by PBL/configuration word after switch to AS = 1 Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Acked-by: Wood Scott-B07421 <B07421@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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fe1a1da0 |
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04-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add networking support to P1023RDS The P1023 has two 1G ethernet controllers the first can run in SGMII, RGMII, or RMII. The second can only do SGMII & RGMII. We need to setup a for SoC & board registers based on our various configuration for ethernet to function properly on the board. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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c916d7c9 |
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13-Apr-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add support for FMan ethernet in Independent mode The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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f110fe94 |
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20-Jul-2011 |
Stephen George <stephen.george@freescale.com> |
powerpc/85xx: Adding configuration for DCSRCR to enable 32M access Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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aeb6716a |
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27-Jun-2011 |
Felix Radensky <felix@embedded-sol.com> |
powerpc/85xx: Fix pin muxing for second USB controller On P1022/P1013 second USB controller is muxed with second Ethernet controller. The current code to enable second USB fails to properly clear pinmux bits used by ethernet. As a result, Linux freezes when this controller is used. This patch fixes the problem. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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f68d3063 |
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14-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: Extend SERDES9 erratum work-around to SGMII, SRIO, and AURORA Part of the SERDES9 erratum work-around is to set some bits in the SerDes TTLCR0 register for lanes configured as XAUI, SGMII, SRIO, or AURORA. The current code does this only for XAUI, so extend it to the other protocols. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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86221f09 |
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12-Apr-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020 The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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e02aea61 |
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08-Feb-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code) The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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df8af0b4 |
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31-Aug-2010 |
Emil Medve <Emilian.Medve@freescale.com> |
p4080/serdes: Implement the XAUI workaround for SERDES9 erratum Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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2bad42a0 |
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09-Apr-2011 |
Ramneek Mehresh <ramneek.mehresh@freescale.com> |
powerpc/85xx: Add support for 2nd USB controller on p1_p2_rdb Second USB controller only works for SPI and SD boot because of pin muxing Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
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4b77047c |
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22-Mar-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Added PMUXCR1 and PMUXCR2 defines for P1010/P1014 SoC Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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b93f81a4 |
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03-Mar-2011 |
Jiang Yutang <b14898@freescale.com> |
powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DS For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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4aa8405c |
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27-Jan-2011 |
Zhao Chenhui <b35336@freescale.com> |
powerpc/85xx: Add some defines & registers in immap_85xx.h * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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a52d2f81 |
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11-Feb-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Add P1021 specific QE and UEC support P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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24995d82 |
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20-Jan-2011 |
Haiying Wang <Haiying.Wang@freescale.com> |
powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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67a719da |
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03-Feb-2011 |
Roy Zang <tie-fei.zang@freescale.com> |
powerpc/85xx: Add support for Freescale P1023/P1017 Processors Add P1023 (dual core) & P1017 (single core) specific information: * SERDES Table * Added P1023/P1017 to cpu_type_list and SVR list (fixed issue with P1013 not being sorted correctly). * Added P1023/P1027 to config_mpc85xx.h * Added new LAW type introduced on P1023/P1017 * Updated a few immap register/defines unique to P1023/P1017 Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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d789b5f5 |
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20-Jan-2011 |
Dipen Dudhat <Dipen.Dudhat@freescale.com> |
powerpc/85xx: Add support for Integrated Flash Controller (IFC) The Integrated Flash Controller (IFC) is used to access the external NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip selects are provided in IFC so that maximum of four Flash devices can be hooked, but only one can be accessed at a given time. Features supported by IFC are, - Functional muxing of pins between NAND, NOR and GPCM - Support memory banks of size 64KByte to 4 GBytes - Write protection capability (only for NAND and NOR) - Provision of Software Reset - Flexible Timing programmability for every chip select - NAND Machine - x8/ x16 NAND Flash Interface - SLC and MLC NAND Flash devices support with configurable page sizes of upto 4KB - Internal SRAM of 9KB which is directly mapped and availble at boot time for NAND Boot - Configurable block size - Boot chip select (CS0) available at system reset - NOR Machine - Data bus width of 8/16/32 - Compatible with asynchronous NOR Flash - Directly memory mapped - Supports address data multiplexed (ADM) NOR device - Boot chip select (CS0) available at system reset - GPCM Machine (NORMAL GPCM Mode) - Support for x8/16/32 bit device - Compatible with general purpose addressable device e.g. SRAM, ROM - External clock is supported with programmable division ratio - GPCM Machine (Generic ASIC Mode) - Support for x8/16/32 bit device - Address and Data are shared on I/O bus - Following Address and Data sequences can be supported on I/O bus - 32 bit I/O: AD - 16 bit I/O: AADD - 8 bit I/O : AAAADDDD - Configurable Even/Odd Parity on Address/Data bus supported Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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28747f9b |
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20-Jan-2011 |
Prabhakar Kushwaha <prabhakar@freescale.com> |
powerpc/85xx: Add SERDES support for P1010/P1014 Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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d2a9568c |
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09-Jan-2011 |
York Sun <yorksun@freescale.com> |
mpc85xx: Adding more registers and options This patch exposes more registers which can be used by the DDR drivers or interactive debugging. U-boot doesn't use all the registers in DDRC. When advanced tuning is required, writing to those registers is needed. Add writing to cdr1, cdr2, err_disable, err_int_en and debug registers Add options to override rcw, address parity to RDIMMs. Use array for debug registers. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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17028be2 |
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17-Jan-2011 |
Prabhakar <prabhakar@freescale.com> |
Fix wrong CONFIG_SYS_MPC85xx_SERDES1_ADDR CONFIG_SYS_MPC85xx_SERDES1_ADDR was defined wrong as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET. It should be as CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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868da593 |
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13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A003 (enable on P4080) CoreNet Platform Cache single-bit data error scrubbing will cause data corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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1d2c2a62 |
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13-Jan-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add the workaround for erratum CPC-A002 (enable on P4080) CoreNet Platform Cache single-bit tag error scrubbing will cause tag corruption. Disable the feature to workaround the issue. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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3c6a22b9 |
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23-Sep-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/p4080: Add new CPC register - HDBCR0 Manual was updated to add a new register for disabling CDQ speculation. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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ed062e0f |
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17-Aug-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs Official docs call it the Job Ring not Job Queue for the p4080 security block. Match the docs to reduce confusion. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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680c613a |
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09-Aug-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: share PIC defines among 85xx and 86xx fixes breakeage introduced by commit a37c36f4e70bada297f281b0e542539ad43e50f6 "powerpc/8xxx: query feature reporting register for num cores on unknown cpus" Reported-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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a37c36f4 |
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14-Jul-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: query feature reporting register for num cores on unknown cpus doing so helps avant garde users, such as those using simulators that allow users to configure the number of cores, so as to not have to manually adjust u-boot sources. h/w should also be reliably setting FRR NCPU in the future. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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ebd7cb0b |
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02-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/fsl_fman: Add initial fman immap structures Add basic structures for Frame Manager on P4080/P3041/P5020 devices Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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9ab87d04 |
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28-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Add additional p4080 platform related defines/structs * Added PCIE4 address, offset, DEVDISR & LAW target ID * Added new p4080 DDR registers and defines to immap * Add missing corenet platform DEVDISR related defines * Updated ccsr_gur to include LIODN registers * Add RCWSR defines * Added Basic qman, pme, bman immap structs * Added SATA related offsets & addresses * Added Frame Manager 1/2 offsets & addresses * Renamed CONFIG_SYS_TSEC1_OFFSET to CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET * Added various offsets and addresses that where missing Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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99d9c07e |
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08-Jul-2010 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Move PCI/PCIe address defines into common immap_85xx.h Remove dupliacted setting of PCI/PCIe address and offsets in board config.h. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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f51cdaf1 |
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17-Jun-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
83xx/85xx/86xx: LBC register cleanup Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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22f292c7 |
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31-May-2010 |
Kim Phillips <kim.phillips@freescale.com> |
powerpc/8xxx: Add base support for the SEC4 Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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6e37a044 |
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19-May-2010 |
Timur Tabi <timur@freescale.com> |
fsl/85xx: add clkdvdr and pmuxcr2 to global utilities structure definition Add the 'clkdvdr' and 'pmuxcr2' registers to the 85xx definition of struct ccsr_gur. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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0c955daf |
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14-Apr-2010 |
Dave Liu <daveliu@freescale.com> |
85xx: clean up the io_sel for PCI express of P1022 clean up the wrong io_sel for PCI express according to latest manual. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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1231c498 |
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07-Apr-2010 |
Kumar Gala <galak@kernel.crashing.org> |
ppc/p4080: Add p4080 DEVDISR2 & SRDS_PLLCR0 defines Added some needed fines and some misc additional defines used by p4080 initialization. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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17d90f31 |
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04-Mar-2010 |
Dave Liu <daveliu@freescale.com> |
ppc/p4080: Extend the GUTS memory map Extend pin control and clock control to GUTS memory map Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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ab48ca1a |
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10-Feb-2010 |
Srikanth Srinivasan <srikanth.srinivasan@freescale.com> |
ppc/p4080: Fix synchronous frequency calculations When DDR is in synchronous mode, the existing code assigns sysclk frequency to DDR frequency. It should be synchronous with the platform frequency. CPU frequency is based on platform frequency in synchronous mode. Also fix: * Fixes the bit mask for DDR_SYNC (RCWSR5[184]) * Corrects the detection of synchronous mode. Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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a47a12be |
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15-Apr-2010 |
Stefan Roese <sr@denx.de> |
Move arch/ppc to arch/powerpc As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
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