1/*
2 * ARC Build Configuration Registers, with encoded hardware config
3 *
4 * Copyright (C) 2018 Synopsys
5 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __ARC_BCR_H
13#define __ARC_BCR_H
14#ifndef __ASSEMBLY__
15
16union bcr_di_cache {
17	struct {
18#ifdef CONFIG_CPU_BIG_ENDIAN
19		unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
20#else
21		unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
22#endif
23	} fields;
24	unsigned int word;
25};
26
27union bcr_slc_cfg {
28	struct {
29#ifdef CONFIG_CPU_BIG_ENDIAN
30		unsigned int pad:24, way:2, lsz:2, sz:4;
31#else
32		unsigned int sz:4, lsz:2, way:2, pad:24;
33#endif
34	} fields;
35	unsigned int word;
36};
37
38union bcr_generic {
39	struct {
40#ifdef CONFIG_CPU_BIG_ENDIAN
41		unsigned int pad:24, ver:8;
42#else
43		unsigned int ver:8, pad:24;
44#endif
45	} fields;
46	unsigned int word;
47};
48
49union bcr_clust_cfg {
50	struct {
51#ifdef CONFIG_CPU_BIG_ENDIAN
52		unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
53#else
54		unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
55#endif
56	} fields;
57	unsigned int word;
58};
59
60union bcr_mmu_4 {
61	struct {
62#ifdef CONFIG_CPU_BIG_ENDIAN
63	unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
64		     n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
65#else
66	/*           DTLB      ITLB      JES        JE         JA      */
67	unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
68		     pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
69#endif
70	} fields;
71	unsigned int word;
72};
73
74#endif /* __ASSEMBLY__ */
75#endif /* __ARC_BCR_H */
76