Searched refs:secure (Results 1 - 25 of 27) sorted by relevance

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/u-boot/arch/arm/mach-uniphier/
H A Dreset.c10 #include <asm/secure.h>
/u-boot/arch/arm/mach-renesas/
H A Dpsci-r8a779a0.c11 #include <asm/secure.h>
/u-boot/arch/arm/cpu/armv7/
H A Dexception_level.c3 * Switch to non-secure mode
8 * secure mode before booting an operating system.
16 #include <asm/secure.h>
20 * entry_non_secure() - entry point when switching to non-secure mode
22 * When switching to non-secure mode switch_to_non_secure_mode() calls this
31 debug("Reached non-secure mode\n");
38 * switch_to_non_secure_mode() - switch to non-secure mode
40 * Operating systems may expect to run in non-secure mode. Here we check if
41 * we are running in secure mode and switch to non-secure mod
[all...]
H A Dpsci-common.c24 #include <asm/secure.h>
H A Dvirt-v7.c6 * Routines to transition ARMv7 processors from secure into non-secure state
7 * and from non-secure SVC into HYP mode
17 #include <asm/secure.h>
104 * according to the spec one should not tinker with it in secure state
105 * in SVC mode. Do not try to read it once in non-secure state,
121 * from non-secure state. The first 32 interrupts are private per
130 * Relocate secure section before any cpu runs in secure ram.
131 * smp_kick_all_cpus may enable other cores and runs into secure
[all...]
H A Dnonsec_virt.S3 * code for switching cores into non-secure state and into HYP mode
20 /* the vector table for secure state and HYP mode */
38 * secure monitor handler
41 * to non-secure state.
51 @ Obtain a secure stack
77 @ FIQ preserved for secure mode
104 movs pc, lr @ ERET to non-secure
139 * of the non-secure and HYP mode transition. The GIC distributor specific
155 * Switch a core to non-secure state.
158 * 2. allow coprocessor access in non-secure mode
[all...]
H A Dpsci.S137 @ Switch to secure
155 @ Switch back to non-secure
/u-boot/arch/arm/mach-omap2/
H A Dutils.c58 const char *secure; local
63 secure = "EMU";
66 secure = "HS";
69 secure = "GP";
72 secure = NULL;
73 printf("Warning: fastboot.secure: unknown CPU sec: %u\n", dev);
76 env_set("fastboot.secure", secure);
H A Dconfig_secure.mk23 "variable must be defined for TI secure devices. \
30 ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),)
31 cmd_omapsecureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \
36 "$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \
41 "variable must be defined for TI secure devices." \
101 # order to secure them in some way
/u-boot/board/kontron/sl28/
H A Dpsci.c3 #include <asm/secure.h>
/u-boot/arch/arm/cpu/armv8/
H A Dcpu.c19 #include <asm/secure.h>
H A Dpsci.S11 #include <asm/secure.h>
/u-boot/drivers/power/domain/
H A DMakefile15 obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o
/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_sfr.h24 u32 secure; /* 0x28: Security Configuration Register */ member in struct:atmel_sfr
/u-boot/board/freescale/common/
H A Darm_sleep.c10 #error " Deep sleep needs non-secure mode support. "
12 #include <asm/secure.h>
/u-boot/arch/arm/mach-uniphier/arm32/
H A Dpsci.c17 #include <asm/secure.h>
/u-boot/arch/arm/mach-tegra/
H A Dpsci.S46 @ lock reset vector for non-secure
/u-boot/include/firmware/imx/sci/
H A Dsci.h105 int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure,
268 static inline int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, argument
/u-boot/arch/arm/mach-imx/imx8m/
H A Dpsci.c12 #include <asm/secure.h>
/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c18 #include <asm/secure.h>
272 /* Switch to secure mode */
353 /* Be cool with non-secure */
/u-boot/arch/arm/lib/
H A Dbootm.c31 #include <asm/secure.h>
/u-boot/board/xilinx/zynqmp/
H A Dcmds.c61 printf("Failed: secure op status:0x%x\n", ret);
343 U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""),
385 "secure src len [key_addr] - verifies secure images of $len bytes\n"
/u-boot/arch/arm/mach-socfpga/
H A Dmailbox_s10.c13 #include <asm/secure.h>
/u-boot/drivers/misc/imx8/
H A Dscu_api.c651 int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, argument
663 RPC_U8(&msg, 0U) = B2U8(secure);
672 printf("%s: secure:%u isolated:%u restricted:%u grant:%u coherent:%u res:%d\n",
673 __func__, secure, isolated, restricted, grant, coherent,
/u-boot/arch/arm/mach-imx/mx7/
H A Dpsci-mx7.c11 #include <asm/secure.h>
474 * from non-secure state. The first 32 interrupts are private per

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