1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Special Function Register (SFR)
4 *
5 * Copyright (C) 2014 Atmel
6 *		      Bo Shen <voice.shen@atmel.com>
7 */
8
9#ifndef __AT91_SFR_H
10#define __AT91_SFR_H
11
12#include <linux/bitops.h>
13struct atmel_sfr {
14	u32 reserved1;	/* 0x00 */
15	union {
16		u32 ddrcfg;	/* 0x04: DDR Configuration Register */
17		u32 ebicsa;	/* 0x04: EBI Chip Select Register */
18	};
19	u32 reserved2;	/* 0x08 */
20	u32 reserved3;	/* 0x0c */
21	u32 ohciicr;	/* 0x10: OHCI Interrupt Configuration Register */
22	u32 ohciisr;	/* 0x14: OHCI Interrupt Status Register */
23	u32 reserved4[4];	/* 0x18 ~ 0x24 */
24	u32 secure;		/* 0x28: Security Configuration Register */
25	u32 reserved5[5];	/* 0x2c ~ 0x3c */
26	u32 ebicfg;		/* 0x40: EBI Configuration Register */
27	u32 reserved6[2];	/* 0x44 ~ 0x48 */
28	u32 sn0;		/* 0x4c */
29	u32 sn1;		/* 0x50 */
30	u32 aicredir;	/* 0x54 */
31	u32 l2cc_hramc;	/* 0x58 */
32};
33
34/* Register Mapping*/
35#define AT91_SFR_DDRCFG		0x04	/* DDR Configuration Register */
36#define AT91_SFR_CCFG_EBICSA	0x04	/* EBI Chip Select Register */
37/* 0x08 ~ 0x0c: Reserved */
38#define AT91_SFR_OHCIICR	0x10	/* OHCI INT Configuration Register */
39#define AT91_SFR_OHCIISR	0x14	/* OHCI INT Status Register */
40#define AT91_SFR_UTMICKTRIM	0x30	/* UTMI Clock Trimming Register */
41#define AT91_SFR_UTMISWAP	0x3c	/* UTMI DP/DM Pin Swapping Register */
42#define AT91_SFR_LS		0x7c	/* Light Sleep Register */
43#define AT91_SFR_I2SCLKSEL	0x90	/* I2SC Register */
44#define AT91_SFR_WPMR		0xe4	/* Write Protection Mode Register */
45
46/* Bit field in DDRCFG */
47#define ATMEL_SFR_DDRCFG_FDQIEN		0x00010000
48#define ATMEL_SFR_DDRCFG_FDQSIEN	0x00020000
49
50/* Bit field in EBICFG */
51#define AT91_SFR_EBICFG_DRIVE0		(0x3 << 0)
52#define AT91_SFR_EBICFG_DRIVE0_LOW		(0x0 << 0)
53#define AT91_SFR_EBICFG_DRIVE0_MEDIUM		(0x2 << 0)
54#define AT91_SFR_EBICFG_DRIVE0_HIGH		(0x3 << 0)
55#define AT91_SFR_EBICFG_PULL0		(0x3 << 2)
56#define AT91_SFR_EBICFG_PULL0_UP		(0x0 << 2)
57#define AT91_SFR_EBICFG_PULL0_NONE		(0x1 << 2)
58#define AT91_SFR_EBICFG_PULL0_DOWN		(0x3 << 2)
59#define AT91_SFR_EBICFG_SCH0		(0x1 << 4)
60#define AT91_SFR_EBICFG_SCH0_OFF		(0x0 << 4)
61#define AT91_SFR_EBICFG_SCH0_ON			(0x1 << 4)
62#define AT91_SFR_EBICFG_DRIVE1		(0x3 << 8)
63#define AT91_SFR_EBICFG_DRIVE1_LOW		(0x0 << 8)
64#define AT91_SFR_EBICFG_DRIVE1_MEDIUM		(0x2 << 8)
65#define AT91_SFR_EBICFG_DRIVE1_HIGH		(0x3 << 8)
66#define AT91_SFR_EBICFG_PULL1		(0x3 << 10)
67#define AT91_SFR_EBICFG_PULL1_UP		(0x0 << 10)
68#define AT91_SFR_EBICFG_PULL1_NONE		(0x1 << 10)
69#define AT91_SFR_EBICFG_PULL1_DOWN		(0x3 << 10)
70#define AT91_SFR_EBICFG_SCH1		(0x1 << 12)
71#define AT91_SFR_EBICFG_SCH1_OFF		(0x0 << 12)
72#define AT91_SFR_EBICFG_SCH1_ON			(0x1 << 12)
73
74/* Bit field in AICREDIR */
75#define ATMEL_SFR_AICREDIR_NSAIC	0x00000001
76
77/* Bit field in DDRCFG */
78#define ATMEL_SFR_DDRCFG_FDQIEN                0x00010000
79#define ATMEL_SFR_DDRCFG_FDQSIEN       0x00020000
80
81#define AT91_SFR_CCFG_EBI_CSA(cs, val)		((val) << (cs))
82#define AT91_SFR_CCFG_EBI_DBPUC			BIT(8)
83#define AT91_SFR_CCFG_EBI_DBPDC			BIT(9)
84#define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60		BIT(16)
85#define AT91_SFR_CCFG_EBI_DRIVE			BIT(17)
86#define AT91_SFR_CCFG_DQIEN_F			BIT(20)
87#define AT91_SFR_CCFG_NFD0_ON_D16		BIT(24)
88#define AT91_SFR_CCFG_DDR_MP_EN			BIT(25)
89
90#define AT91_SFR_OHCIICR_RES(x)			BIT(x)
91#define AT91_SFR_OHCIICR_ARIE			BIT(4)
92#define AT91_SFR_OHCIICR_APPSTART		BIT(5)
93#define AT91_SFR_OHCIICR_USB_SUSP(x)		BIT(8 + (x))
94#define AT91_SFR_OHCIICR_UDPPUDIS		BIT(23)
95#define AT91_OHCIICR_USB_SUSPEND		GENMASK(10, 8)
96
97#define AT91_SFR_OHCIISR_RIS(x)			BIT(x)
98
99#define AT91_UTMICKTRIM_FREQ			GENMASK(1, 0)
100
101#define AT91_SFR_UTMISWAP_PORT(x)		BIT(x)
102
103#define AT91_SFR_LS_VALUE(x)			BIT(x)
104#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN	BIT(16)
105
106#define AT91_SFR_WPMR_WPEN			BIT(0)
107#define AT91_SFR_WPMR_WPKEY_MASK		GENMASK(31, 8)
108
109#endif
110