1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2018 NXP 4 */ 5 6#ifndef _SC_SCI_H 7#define _SC_SCI_H 8 9#include <log.h> 10#include <firmware/imx/sci/types.h> 11#include <firmware/imx/sci/svc/misc/api.h> 12#include <firmware/imx/sci/svc/pad/api.h> 13#include <firmware/imx/sci/svc/pm/api.h> 14#include <firmware/imx/sci/svc/rm/api.h> 15#include <firmware/imx/sci/svc/seco/api.h> 16#include <firmware/imx/sci/svc/timer/api.h> 17#include <firmware/imx/sci/rpc.h> 18#include <dt-bindings/soc/imx_rsrc.h> 19#include <linux/errno.h> 20 21static inline int sc_err_to_linux(sc_err_t err) 22{ 23 int ret; 24 25 switch (err) { 26 case SC_ERR_NONE: 27 return 0; 28 case SC_ERR_VERSION: 29 case SC_ERR_CONFIG: 30 case SC_ERR_PARM: 31 ret = -EINVAL; 32 break; 33 case SC_ERR_NOACCESS: 34 case SC_ERR_LOCKED: 35 case SC_ERR_UNAVAILABLE: 36 ret = -EACCES; 37 break; 38 case SC_ERR_NOTFOUND: 39 case SC_ERR_NOPOWER: 40 ret = -ENODEV; 41 break; 42 case SC_ERR_IPC: 43 ret = -EIO; 44 break; 45 case SC_ERR_BUSY: 46 ret = -EBUSY; 47 break; 48 case SC_ERR_FAIL: 49 ret = -EIO; 50 break; 51 default: 52 ret = 0; 53 break; 54 } 55 56 debug("%s %d %d\n", __func__, err, ret); 57 58 return ret; 59} 60 61#if IS_ENABLED(CONFIG_IMX8) 62/* PM API*/ 63int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, 64 sc_pm_power_mode_t mode); 65int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, 66 sc_pm_power_mode_t *mode); 67int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, 68 sc_pm_clock_rate_t *rate); 69int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, 70 sc_pm_clock_rate_t *rate); 71int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, 72 sc_bool_t enable, sc_bool_t autog); 73int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, 74 sc_pm_clk_parent_t parent); 75int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, 76 sc_faddr_t address); 77void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); 78int sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); 79sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); 80int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource); 81 82/* MISC API */ 83int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, 84 sc_ctrl_t ctrl, u32 val); 85int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, 86 u32 *val); 87void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); 88void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); 89int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx); 90void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); 91int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); 92int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, 93 s16 *celsius, s8 *tenths); 94void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status); 95 96/* RM API */ 97sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); 98int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, 99 sc_faddr_t addr_end); 100int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, 101 sc_rm_pt_t pt, sc_rm_perm_t perm); 102int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, 103 sc_faddr_t *addr_end); 104sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource); 105int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, 106 sc_bool_t isolated, sc_bool_t restricted, 107 sc_bool_t grant, sc_bool_t coherent); 108int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt); 109int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt); 110int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent); 111int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource); 112int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad); 113sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad); 114int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, 115 sc_rm_pt_t *pt); 116 117/* PAD API */ 118int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); 119int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); 120 121/* SMMU API */ 122int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); 123 124/* Timer API */ 125int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); 126 127/* SECO API */ 128int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, 129 sc_faddr_t addr); 130int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change); 131int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, 132 u32 *uid_h); 133void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); 134int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); 135int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); 136int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, 137 sc_faddr_t export_addr, u16 max_size); 138int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size); 139int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock); 140int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, 141 u16 msg_size, sc_faddr_t dst_addr, u16 dst_size); 142int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data); 143int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, 144 u32 *data0, u32 *data1, u32 *data2, u32 *data3, 145 u32 *data4, u8 size); 146#else 147/* PM API*/ 148static inline int sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, 149 sc_pm_power_mode_t mode) 150{ 151 return -EOPNOTSUPP; 152} 153 154static inline int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, 155 sc_pm_power_mode_t *mode) 156{ 157 return -EOPNOTSUPP; 158} 159 160static inline int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, 161 sc_pm_clock_rate_t *rate) 162{ 163 return -EOPNOTSUPP; 164} 165 166static inline int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, 167 sc_pm_clock_rate_t *rate) 168{ 169 return -EOPNOTSUPP; 170} 171 172static inline int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, 173 sc_bool_t enable, sc_bool_t autog) 174{ 175 return -EOPNOTSUPP; 176} 177 178static inline int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, 179 sc_pm_clk_parent_t parent) 180{ 181 return -EOPNOTSUPP; 182} 183 184static inline int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, 185 sc_faddr_t address) 186{ 187 return -EOPNOTSUPP; 188} 189 190static inline sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt) 191{ 192 return false; 193} 194 195static inline int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource) 196{ 197 return -EOPNOTSUPP; 198} 199 200/* MISC API */ 201static inline int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 val) 202{ 203 return -EOPNOTSUPP; 204} 205 206static inline int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 *val) 207{ 208 return -EOPNOTSUPP; 209} 210 211static inline void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev) 212{ 213} 214 215static inline void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) 216{ 217} 218 219static inline int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx) 220{ 221 return -EOPNOTSUPP; 222} 223 224static inline void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit) 225{ 226} 227 228static inline int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val) 229{ 230 return -EOPNOTSUPP; 231} 232 233static inline int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, 234 s16 *celsius, s8 *tenths) 235{ 236 return -EOPNOTSUPP; 237} 238 239/* RM API */ 240static inline sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) 241{ 242 return true; 243} 244 245static inline int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start, 246 sc_faddr_t addr_end) 247{ 248 return -EOPNOTSUPP; 249} 250 251static inline int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr, sc_rm_pt_t pt, 252 sc_rm_perm_t perm) 253{ 254 return -EOPNOTSUPP; 255} 256 257static inline int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start, 258 sc_faddr_t *addr_end) 259{ 260 return -EOPNOTSUPP; 261} 262 263static inline sc_bool_t sc_rm_is_resource_owned(sc_ipc_t ipc, sc_rsrc_t resource) 264{ 265 return true; 266} 267 268static inline int sc_rm_partition_alloc(sc_ipc_t ipc, sc_rm_pt_t *pt, sc_bool_t secure, 269 sc_bool_t isolated, sc_bool_t restricted, 270 sc_bool_t grant, sc_bool_t coherent) 271{ 272 return -EOPNOTSUPP; 273} 274 275static inline int sc_rm_partition_free(sc_ipc_t ipc, sc_rm_pt_t pt) 276{ 277 return -EOPNOTSUPP; 278} 279 280static inline int sc_rm_get_partition(sc_ipc_t ipc, sc_rm_pt_t *pt) 281{ 282 return -EOPNOTSUPP; 283} 284 285static inline int sc_rm_set_parent(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rm_pt_t pt_parent) 286{ 287 return -EOPNOTSUPP; 288} 289 290static inline int sc_rm_assign_resource(sc_ipc_t ipc, sc_rm_pt_t pt, sc_rsrc_t resource) 291{ 292 return -EOPNOTSUPP; 293} 294 295static inline int sc_rm_assign_pad(sc_ipc_t ipc, sc_rm_pt_t pt, sc_pad_t pad) 296{ 297 return -EOPNOTSUPP; 298} 299 300static inline sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) 301{ 302 return true; 303} 304 305static inline int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_pt_t *pt) 306{ 307 return -EOPNOTSUPP; 308} 309 310/* PAD API */ 311static inline int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val) 312{ 313 return -EOPNOTSUPP; 314} 315 316static inline int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val) 317{ 318 return -EOPNOTSUPP; 319} 320 321/* SMMU API */ 322static inline int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid) 323{ 324 return -EOPNOTSUPP; 325} 326 327/* SECO API */ 328static inline int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) 329{ 330 return -EOPNOTSUPP; 331} 332 333static inline int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change) 334{ 335 return -EOPNOTSUPP; 336} 337 338static inline int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, u32 *uid_h) 339{ 340 return -EOPNOTSUPP; 341} 342 343void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) 344{ 345} 346 347static inline int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event) 348{ 349 return -EOPNOTSUPP; 350} 351 352static inline int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, 353 sc_faddr_t export_addr, u16 max_size) 354{ 355 return -EOPNOTSUPP; 356} 357 358static inline int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size) 359{ 360 return -EOPNOTSUPP; 361} 362 363static inline int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock) 364{ 365 return -EOPNOTSUPP; 366} 367 368static inline int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, u16 msg_size, 369 sc_faddr_t dst_addr, u16 dst_size) 370{ 371 return -EOPNOTSUPP; 372} 373 374static inline int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data) 375{ 376 return -EOPNOTSUPP; 377} 378 379static inline int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data0, u32 *data1, 380 u32 *data2, u32 *data3, u32 *data4, u8 size) 381{ 382 return -EOPNOTSUPP; 383} 384 385static inline void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) 386{ 387} 388 389static inline int sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason) 390{ 391 return -EOPNOTSUPP; 392} 393 394static inline int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) 395{ 396 return -EOPNOTSUPP; 397} 398 399static inline void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) 400{ 401} 402 403static inline int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) 404{ 405 return -EOPNOTSUPP; 406} 407#endif 408 409#endif 410