/u-boot/arch/arm/mach-uniphier/dram/ |
H A D | ddrphy-init.h | 12 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus); 13 void ddrphy_prepare_training(void __iomem *phy_base, int rank); 14 int ddrphy_training(void __iomem *phy_base);
|
H A D | ddrphy-ld4.c | 31 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus) argument 48 writel(0x0300c473, phy_base + PHY_PGCR1); 49 writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); 50 writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1); 51 writel(0x00083DEF, phy_base + PHY_PTR2); 52 writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3); 53 writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4); 54 writel(0xF004001A, phy_base + PHY_DSGCR); 57 tmp = readl(phy_base + PHY_DXCCR); 60 writel(tmp, phy_base [all...] |
H A D | umc-pxs2.c | 60 static void ddrphy_fifo_reset(void __iomem *phy_base) argument 64 tmp = readl(phy_base + MPHY_PGCR0); 66 writel(tmp, phy_base + MPHY_PGCR0); 71 writel(tmp, phy_base + MPHY_PGCR0); 76 static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable) argument 80 tmp = readl(phy_base + MPHY_PGCR1); 87 writel(tmp, phy_base + MPHY_PGCR1); 90 while (!(readl(phy_base + MPHY_PGSR1) & MPHY_PGSR1_VTSTOP)) 95 static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step) argument 99 void __iomem *dx_base = phy_base 116 ddrphy_get_system_latency(void __iomem *phy_base, int width) argument 144 ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width, int ch) argument 312 __ddrphy_training(void __iomem *phy_base, const struct ddrphy_init_sequence *seq) argument 356 ddrphy_impedance_calibration(void __iomem *phy_base) argument 383 ddrphy_dram_init(void __iomem *phy_base) argument 388 ddrphy_training(void __iomem *phy_base) argument 548 void __iomem *phy_base = umc_ch_base + 0x00030000; local [all...] |
H A D | ddrphy-training.c | 21 void ddrphy_prepare_training(void __iomem *phy_base, int rank) argument 23 void __iomem *dx_base = phy_base + PHY_DX_BASE; 37 tmp = readl(phy_base + PHY_DTCR); 46 writel(tmp, phy_base + PHY_DTCR); 107 int ddrphy_training(void __iomem *phy_base) argument 123 writel(init_flag, phy_base + PHY_PIR); 131 pgsr0 = readl(phy_base + PHY_PGSR0);
|
H A D | cmd_ddrmphy.c | 73 void __iomem *phy_base, *dx_base; local 77 phy_base = ioremap(param->phy[phy].base, SZ_4K); 78 dx_base = phy_base + MPHY_DX_BASE; 87 iounmap(phy_base); 93 void __iomem *phy_base, *zq_base; local 101 phy_base = ioremap(param->phy[phy].base, SZ_4K); 102 zq_base = phy_base + MPHY_ZQ_BASE; 123 iounmap(phy_base); 229 { int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \ 236 void __iomem *reg = phy_base 242 void __iomem *phy_base; local [all...] |
H A D | cmd_ddrphy.c | 88 void __iomem *phy_base, *dx_base; local 92 phy_base = ioremap(param->phy[phy].base, SZ_4K); 93 dx_base = phy_base + PHY_DX_BASE; 102 iounmap(phy_base); 203 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \ 211 void __iomem *reg = phy_base + ofst; \ 218 void __iomem *phy_base; local 224 phy_base = ioremap(param->phy[phy].base, SZ_4K); 227 phy, ptr_to_uint(phy_base)); 260 iounmap(phy_base); [all...] |
H A D | umc-pro4.c | 134 void __iomem *phy_base = dc_base + 0x00001000; local 146 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); 150 ddrphy_prepare_training(phy_base, phy); 151 ret = ddrphy_training(phy_base); 155 phy_base += 0x00001000;
|
H A D | umc-sld8.c | 150 void __iomem *phy_base = dc_base + 0x00001000; local 159 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); 163 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); 164 ret = ddrphy_training(phy_base);
|
H A D | umc-ld4.c | 147 void __iomem *phy_base = dc_base + 0x00001000; local 156 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); 160 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); 161 ret = ddrphy_training(phy_base);
|
/u-boot/drivers/ram/rockchip/ |
H A D | sdram_phy_px30.c | 14 static void sdram_phy_dll_bypass_set(void __iomem *phy_base, u32 freq) argument 20 setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4); 21 clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3); 24 setbits_le32(PHY_REG(phy_base, j), 1 << 4); 25 clrbits_le32(PHY_REG(phy_base, j + 0x1), 1 << 3); 30 setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); 32 clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); 47 writel(tmp, PHY_REG(phy_base, j)); 51 static void sdram_phy_set_ds_odt(void __iomem *phy_base, argument 72 writel(cmd_drv, PHY_REG(phy_base, 87 phy_soft_reset(void __iomem *phy_base) argument 97 phy_dram_set_bw(void __iomem *phy_base, u32 bw) argument 117 phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype) argument 171 phy_cfg(void __iomem *phy_base, struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew, struct sdram_base_params *base, u32 bw) argument [all...] |
H A D | sdram_rv1126.c | 542 void __iomem *phy_base = dram->phy; local 546 clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB); 547 while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) 565 writel(fbdiv & 0xff, PHY_REG(phy_base, 0x50)); 566 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, 568 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, 571 clrsetbits_le32(PHY_REG(phy_base, 0x52), 573 clrsetbits_le32(PHY_REG(phy_base, 0x53), 853 void __iomem *phy_base = dram->phy; local 1010 clrsetbits_le32(PHY_REG(phy_base, 1194 void __iomem *phy_base = dram->phy; local 1215 void __iomem *phy_base = dram->phy; local 1344 void __iomem *phy_base = dram->phy; local 1367 void __iomem *phy_base = dram->phy; local 1377 void __iomem *phy_base = dram->phy; local 1388 void __iomem *phy_base = dram->phy; local 1405 void __iomem *phy_base = dram->phy; local 1456 void __iomem *phy_base = dram->phy; local 1506 void __iomem *phy_base = dram->phy; local 1545 void __iomem *phy_base = dram->phy; local 1597 void __iomem *phy_base = dram->phy; local 1667 void __iomem *phy_base = dram->phy; local 1784 void __iomem *phy_base = dram->phy; local 1942 void __iomem *phy_base = dram->phy; local 1968 init_rw_trn_result_struct(struct rw_trn_result *result, void __iomem *phy_base, u8 cs_num) argument 1980 save_rw_trn_min_max(void __iomem *phy_base, struct cs_rw_trn_result *rd_result, struct cs_rw_trn_result *wr_result, u8 byte_en) argument 2010 save_rw_trn_deskew(void __iomem *phy_base, struct fsp_rw_trn_result *result, u8 cs_num, int min_val, bool rw) argument 2057 void __iomem *phy_base = dram->phy; local 2356 void __iomem *phy_base = dram->phy; local 2475 void __iomem *phy_base = dram->phy; local 2808 void __iomem *phy_base = dram->phy; local 2932 void __iomem *phy_base = dram->phy; local 3178 void __iomem *phy_base = dram->phy; local [all...] |
H A D | sdram_rk3328.c | 122 void __iomem *phy_base = dram->phy; local 125 clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7); 261 void __iomem *phy_base = dram->phy; local 264 gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val); 268 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2); 269 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4, 275 void __iomem *phy_base = dram->phy; local 277 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1);
|
H A D | sdram_px30.c | 318 void __iomem *phy_base = dram->phy; local 325 bw = (readl(PHY_REG(phy_base, 0x0)) >> 4) & 0xf; 340 gate[i] = readl(PHY_REG(phy_base, 0xfb + i)); 436 void __iomem *phy_base = dram->phy; local 463 setbits_le32(PHY_REG(phy_base, 7), 1 << 7);
|
/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | sdram_phy_px30.h | 59 void phy_soft_reset(void __iomem *phy_base); 60 void phy_dram_set_bw(void __iomem *phy_base, u32 bw); 61 void phy_cfg(void __iomem *phy_base, 64 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype);
|
/u-boot/arch/arm/mach-mvebu/alleycat5/ |
H A D | soc.c | 271 u64 new_val, phy_base = 0x7F080800; local 279 for (phy_i = 0; phy_i < 2; phy_i++, phy_base += USB_STEPPING) { 280 WRITE_MASK(phy_base + 0x4, 0x3, 0x2); 281 WRITE_MASK(phy_base + 0xC, 0x3000000, 0x2000000); 282 WRITE_MASK(phy_base + 0x1C, 0x3, 0x2); 283 WRITE_MASK(phy_base + 0x0, 0x1FF007F, 0x600005); 284 WRITE_MASK(phy_base + 0xC, 0x000F000, 0x0002000); 286 WRITE_MASK(phy_base + 0x8, 0x700, 0x400) 287 WRITE_MASK(phy_base + 0x14, 0x000000F, 0x000000a); 289 WRITE_MASK(phy_base [all...] |
/u-boot/drivers/ddr/altera/ |
H A D | sdram_n5x.c | 360 phys_addr_t phy_base; member in struct:ddr_handoff 775 if (ddr_handoff_info && base == ddr_handoff_info->phy_base) { 952 ddr_handoff_info->phy_base); 965 handoff->phy_engine_handoff_length, handoff->phy_base); 1093 handoff->phy_base = readl(handoff->phy_handoff_base + 1096 (u32)handoff->phy_base); 1172 handoff->train_imem_base = handoff->phy_base + 1177 handoff->train_dmem_base = handoff->phy_base + 1387 (uintptr_t)(ddr_handoff_info->phy_base + 1391 clrbits_le16(ddr_handoff_info->phy_base [all...] |
/u-boot/drivers/phy/ |
H A D | omap-usb2-phy.c | 48 void *phy_base; member in struct:omap_usb2_phy 165 val = readl(priv->phy_base + USB2PHY_ANA_CONFIG1); 167 writel(val, priv->phy_base + USB2PHY_ANA_CONFIG1); 171 val = readl(priv->phy_base + USB2PHY_CHRG_DET); 173 writel(val, priv->phy_base + USB2PHY_CHRG_DET); 218 priv->phy_base = dev_read_addr_ptr(dev); 220 if (!priv->phy_base)
|
/u-boot/drivers/usb/host/ |
H A D | xhci-exynos5.c | 40 fdt_addr_t phy_base; member in struct:exynos_xhci_plat 83 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); 84 if (plat->phy_base == FDT_ADDR_T_NONE) { 215 ctx->usb3_phy = (struct exynos_usb3_phy *)plat->phy_base;
|
H A D | ehci-exynos.c | 33 fdt_addr_t phy_base; member in struct:exynos_ehci_plat 74 plat->phy_base = fdtdec_get_addr(blob, node, "reg"); 75 if (plat->phy_base == FDT_ADDR_T_NONE) { 223 ctx->usb = (struct exynos_usb_phy *)plat->phy_base;
|
/u-boot/drivers/phy/rockchip/ |
H A D | phy-rockchip-inno-dsidphy.c | 215 void __iomem *phy_base; member in struct:inno_dsidphy 293 orig = readl(inno->phy_base + reg); 296 writel(tmp, inno->phy_base + reg); 627 inno->phy_base = dev_read_addr_ptr(dev); 628 if (IS_ERR(inno->phy_base)) 629 return PTR_ERR(inno->phy_base);
|