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d678a59d |
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18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
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0e34e80f |
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30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: mvebu: Remove <common.h> and add needed includes Remove <common.h> from all mach-mvebu files and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
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f52e2d88 |
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09-Jul-2023 |
Chris Packham <judge.packham@gmail.com> |
arm: mvebu: ac5: Define mvebu_get_nand_clock() The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping or gating require so just add a mvebu_get_nand_clock() that returns this value. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
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f47c765d |
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15-Feb-2023 |
Tom Rini <trini@konsulko.com> |
mvebe: Drop ARCH_MISC_INIT from alleycat 5 In this platform, arch_misc_init doesn't perform any real function. The call to get_soc_type_rev has no lasting side effects. Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> |
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7d7bb99e |
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04-Nov-2022 |
Chris Packham <judge.packham@gmail.com> |
arm: mvebu: Support for 98DX25xx/98DX35xx SoC Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com> |
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0e34e80f |
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30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: mvebu: Remove <common.h> and add needed includes Remove <common.h> from all mach-mvebu files and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
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f52e2d88 |
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09-Jul-2023 |
Chris Packham <judge.packham@gmail.com> |
arm: mvebu: ac5: Define mvebu_get_nand_clock() The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping or gating require so just add a mvebu_get_nand_clock() that returns this value. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
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f47c765d |
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15-Feb-2023 |
Tom Rini <trini@konsulko.com> |
mvebe: Drop ARCH_MISC_INIT from alleycat 5 In this platform, arch_misc_init doesn't perform any real function. The call to get_soc_type_rev has no lasting side effects. Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> |
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7d7bb99e |
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04-Nov-2022 |
Chris Packham <judge.packham@gmail.com> |
arm: mvebu: Support for 98DX25xx/98DX35xx SoC Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com> |
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f52e2d88 |
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09-Jul-2023 |
Chris Packham <judge.packham@gmail.com> |
arm: mvebu: ac5: Define mvebu_get_nand_clock() The NF_CLK for the AC5 SoC runs at 400MHz. There's no strapping or gating require so just add a mvebu_get_nand_clock() that returns this value. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> |
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f47c765d |
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15-Feb-2023 |
Tom Rini <trini@konsulko.com> |
mvebe: Drop ARCH_MISC_INIT from alleycat 5 In this platform, arch_misc_init doesn't perform any real function. The call to get_soc_type_rev has no lasting side effects. Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> |
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7d7bb99e |
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04-Nov-2022 |
Chris Packham <judge.packham@gmail.com> |
arm: mvebu: Support for 98DX25xx/98DX35xx SoC Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com> |
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f47c765d |
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15-Feb-2023 |
Tom Rini <trini@konsulko.com> |
mvebe: Drop ARCH_MISC_INIT from alleycat 5 In this platform, arch_misc_init doesn't perform any real function. The call to get_soc_type_rev has no lasting side effects. Cc: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> |
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7d7bb99e |
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04-Nov-2022 |
Chris Packham <judge.packham@gmail.com> |
arm: mvebu: Support for 98DX25xx/98DX35xx SoC Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com> |
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7d7bb99e |
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04-Nov-2022 |
Chris Packham <judge.packham@gmail.com> |
arm: mvebu: Support for 98DX25xx/98DX35xx SoC Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with an integrated CPU (referred to as the CnM block in Marvell's documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support has been ported from Marvell's SDK which is based on a much older version of U-Boot. Signed-off-by: Chris Packham <judge.packham@gmail.com> |