1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2011-2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 */
7
8#include <linux/errno.h>
9#include <linux/io.h>
10#include <linux/printk.h>
11#include <linux/sizes.h>
12#include <asm/processor.h>
13
14#include "../init.h"
15#include "ddrphy-init.h"
16#include "umc-regs.h"
17
18#define DRAM_CH_NR	2
19
20enum dram_size {
21	DRAM_SZ_128M,
22	DRAM_SZ_256M,
23	DRAM_SZ_512M,
24	DRAM_SZ_NR,
25};
26
27static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
28
29static void umc_start_ssif(void __iomem *ssif_base)
30{
31	writel(0x00000000, ssif_base + 0x0000b004);
32	writel(0xffffffff, ssif_base + 0x0000c004);
33	writel(0x000fffcf, ssif_base + 0x0000c008);
34	writel(0x00000001, ssif_base + 0x0000b000);
35	writel(0x00000001, ssif_base + 0x0000c000);
36
37	writel(0x03010100, ssif_base + UMC_HDMCHSEL);
38	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
39	writel(0x03010100, ssif_base + UMC_DVCCHSEL);
40	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
41
42	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
43	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
44	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
45	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
46	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
47	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
48	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
49	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
50	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
51	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
52	writel(0x00000000, ssif_base + 0x0000c044);		/* DCGIV_SSIF_REG */
53
54	writel(0x00000001, ssif_base + UMC_CPURST);
55	writel(0x00000001, ssif_base + UMC_IDSRST);
56	writel(0x00000001, ssif_base + UMC_IXMRST);
57	writel(0x00000001, ssif_base + UMC_HDMRST);
58	writel(0x00000001, ssif_base + UMC_MDMRST);
59	writel(0x00000001, ssif_base + UMC_HDDRST);
60	writel(0x00000001, ssif_base + UMC_MDDRST);
61	writel(0x00000001, ssif_base + UMC_SIORST);
62	writel(0x00000001, ssif_base + UMC_GIORST);
63	writel(0x00000001, ssif_base + UMC_HD2RST);
64	writel(0x00000001, ssif_base + UMC_VIORST);
65	writel(0x00000001, ssif_base + UMC_DVCRST);
66	writel(0x00000001, ssif_base + UMC_RGLRST);
67	writel(0x00000001, ssif_base + UMC_VPERST);
68	writel(0x00000001, ssif_base + UMC_AIORST);
69	writel(0x00000001, ssif_base + UMC_DMDRST);
70}
71
72static int umc_dramcont_init(void __iomem *dc_base, void __iomem *ca_base,
73			     int freq, unsigned long size, bool ddr3plus)
74{
75	enum dram_size size_e;
76
77	if (freq != 1600) {
78		pr_err("Unsupported DDR frequency %d MHz\n", freq);
79		return -EINVAL;
80	}
81
82	if (ddr3plus) {
83		pr_err("DDR3+ is not supported\n");
84		return -EINVAL;
85	}
86
87	switch (size) {
88	case SZ_128M:
89		size_e = DRAM_SZ_128M;
90		break;
91	case SZ_256M:
92		size_e = DRAM_SZ_256M;
93		break;
94	case SZ_512M:
95		size_e = DRAM_SZ_512M;
96		break;
97	default:
98		pr_err("unsupported DRAM size 0x%08lx (per 16bit)\n", size);
99		return -EINVAL;
100	}
101
102	writel(0x66bb0f17, dc_base + UMC_CMDCTLA);
103	writel(0x18c6aa44, dc_base + UMC_CMDCTLB);
104	writel(umc_spcctla[size_e], dc_base + UMC_SPCCTLA);
105	writel(0x00ff0008, dc_base + UMC_SPCCTLB);
106	writel(0x000c00ae, dc_base + UMC_RDATACTL_D0);
107	writel(0x000c00ae, dc_base + UMC_RDATACTL_D1);
108	writel(0x04060802, dc_base + UMC_WDATACTL_D0);
109	writel(0x04060802, dc_base + UMC_WDATACTL_D1);
110	writel(0x04a02000, dc_base + UMC_DATASET);
111	writel(0x00000000, ca_base + 0x2300);
112	writel(0x00400020, dc_base + UMC_DCCGCTL);
113	writel(0x0000000f, dc_base + 0x7000);
114	writel(0x0000000f, dc_base + 0x8000);
115	writel(0x000000c3, dc_base + 0x8004);
116	writel(0x00000071, dc_base + 0x8008);
117	writel(0x00000004, dc_base + UMC_FLOWCTLG);
118	writel(0x00000000, dc_base + 0x0060);
119	writel(0x80000201, ca_base + 0xc20);
120	writel(0x0801e01e, dc_base + UMC_FLOWCTLA);
121	writel(0x00200000, dc_base + UMC_FLOWCTLB);
122	writel(0x00004444, dc_base + UMC_FLOWCTLC);
123	writel(0x200a0a00, dc_base + UMC_SPCSETB);
124	writel(0x00010000, dc_base + UMC_SPCSETD);
125	writel(0x80000020, dc_base + UMC_DFICUPDCTLA);
126
127	return 0;
128}
129
130static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
131		       int freq, unsigned long size, unsigned int width,
132		       bool ddr3plus)
133{
134	void __iomem *phy_base = dc_base + 0x00001000;
135	int nr_phy = width / 16;
136	int phy, ret;
137
138	writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
139	while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
140		cpu_relax();
141
142	for (phy = 0; phy < nr_phy; phy++) {
143		writel(0x00000100 | ((1 << (phy + 1)) - 1),
144		       dc_base + UMC_DIOCTLA);
145
146		ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus);
147		if (ret)
148			return ret;
149
150		ddrphy_prepare_training(phy_base, phy);
151		ret = ddrphy_training(phy_base);
152		if (ret)
153			return ret;
154
155		phy_base += 0x00001000;
156	}
157
158	return umc_dramcont_init(dc_base, ca_base, freq, size / (width / 16),
159				 ddr3plus);
160}
161
162int uniphier_pro4_umc_init(const struct uniphier_board_data *bd)
163{
164	void __iomem *umc_base = (void __iomem *)0x5b800000;
165	void __iomem *ca_base = umc_base + 0x00001000;
166	void __iomem *dc_base = umc_base + 0x00400000;
167	void __iomem *ssif_base = umc_base;
168	int ch, ret;
169
170	for (ch = 0; ch < DRAM_CH_NR; ch++) {
171		ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
172				  bd->dram_ch[ch].size,
173				  bd->dram_ch[ch].width,
174				  !!(bd->flags & UNIPHIER_BD_DDR3PLUS));
175		if (ret) {
176			pr_err("failed to initialize UMC ch%d\n", ch);
177			return ret;
178		}
179
180		ca_base += 0x00001000;
181		dc_base += 0x00200000;
182	}
183
184	umc_start_ssif(ssif_base);
185
186	return 0;
187}
188