1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014      Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
5 */
6
7#include <linux/bitops.h>
8#include <linux/errno.h>
9#include <linux/io.h>
10#include <linux/printk.h>
11
12#include "ddrphy-init.h"
13#include "ddrphy-regs.h"
14
15enum dram_freq {
16	DRAM_FREQ_1333M,
17	DRAM_FREQ_1600M,
18	DRAM_FREQ_NR,
19};
20
21static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
22static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
23static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
24static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
25static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
26static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
27static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
28static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
29static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
30
31int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)
32{
33	enum dram_freq freq_e;
34	u32 tmp;
35
36	switch (freq) {
37	case 1333:
38		freq_e = DRAM_FREQ_1333M;
39		break;
40	case 1600:
41		freq_e = DRAM_FREQ_1600M;
42		break;
43	default:
44		pr_err("unsupported DRAM frequency %d MHz\n", freq);
45		return -EINVAL;
46	}
47
48	writel(0x0300c473, phy_base + PHY_PGCR1);
49	writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);
50	writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);
51	writel(0x00083DEF, phy_base + PHY_PTR2);
52	writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);
53	writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);
54	writel(0xF004001A, phy_base + PHY_DSGCR);
55
56	/* change the value of the on-die pull-up/pull-down registors */
57	tmp = readl(phy_base + PHY_DXCCR);
58	tmp &= ~0x0ee0;
59	tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM;
60	writel(tmp, phy_base + PHY_DXCCR);
61
62	writel(0x0000040B, phy_base + PHY_DCR);
63	writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);
64	writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);
65	writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);
66	writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);
67	writel(0x00000006, phy_base + PHY_MR1);
68	writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);
69	writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);
70
71	while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
72		;
73
74	writel(0x0300C473, phy_base + PHY_PGCR1);
75	writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);
76
77	return 0;
78}
79