/u-boot/drivers/video/ |
H A D | anx9804.h | 19 void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp); 21 static inline void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, argument
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H A D | anx9804.c | 24 * @lanes: Number of displayport lanes to use 28 void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp) 89 /* Power up and configure lanes */ 107 /* Set data-rate / lanes */ 109 dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes); 29 anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp) argument
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H A D | samsung-ltl106hl02.c | 130 plat->lanes = 4;
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H A D | tdo-tl070wsh30.c | 126 plat->lanes = 4;
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/u-boot/include/ |
H A D | phy-mipi-dphy.h | 270 * @lanes: 272 * Number of active, consecutive, data lanes, starting from 275 unsigned char lanes; member in struct:phy_configure_opts_mipi_dphy 280 unsigned int lanes,
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H A D | mipi_dsi.h | 122 u32 lanes, u32 format, unsigned int *lane_mbps); 199 * @lanes: number of active data lanes 208 unsigned int lanes; member in struct:mipi_dsi_device 241 * @lanes: number of active data lanes 247 unsigned int lanes; member in struct:mipi_dsi_panel_plat
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/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
H A D | ls1012a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config 42 return ptr->lanes[lane]; 68 if (ptr->lanes[i] != NONE)
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H A D | ls1043a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config 54 return ptr->lanes[lane]; 80 if (ptr->lanes[i] != NONE)
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H A D | ls1028a_serdes.c | 12 u8 lanes[SRDS_MAX_LANES]; 60 return ptr->lanes[lane]; 86 if (ptr->lanes[i] != NONE) 11 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
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H A D | ls1046a_serdes.c | 13 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config 69 return ptr->lanes[lane]; 95 if (ptr->lanes[i] != NONE)
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H A D | ls1088a_serdes.c | 13 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config 113 return ptr->lanes[lane]; 139 if (ptr->lanes[i] != NONE)
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H A D | lx2160a_serdes.c | 11 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config 118 return ptr->lanes[lane]; 144 if (ptr->lanes[i] != NONE)
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H A D | ls2080a_serdes.c | 11 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config 92 return ptr->lanes[lane]; 118 if (ptr->lanes[i] != NONE)
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/u-boot/drivers/phy/ |
H A D | phy-core-mipi-dphy.c | 20 unsigned int lanes, 30 do_div(hs_clk_rate, lanes); 72 cfg->lanes = lanes; 18 phy_mipi_dphy_get_default_config(unsigned long pixel_clock, unsigned int bpp, unsigned int lanes, struct phy_configure_opts_mipi_dphy *cfg) argument
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/u-boot/arch/powerpc/cpu/mpc85xx/ |
H A D | c29x_serdes.c | 18 u8 lanes[SRDS1_MAX_LANES]; 64 enum srds_prtcl lane_prtcl = ptr->lanes[lane]; 19 u8 lanes[SRDS1_MAX_LANES]; member in struct:serdes_config
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H A D | fsl_corenet_serdes.c | 67 } lanes[SRDS_MAX_LANES] = { variable in typeref:struct:__anon85 101 return lanes[lane].idx; 106 return lanes[lane].bank; 114 int bank = lanes[lane].bank; 115 int word = lanes[lane].lpd / 32; 116 int bit = lanes[lane].lpd % 32; 278 * want to enable the bank, whether we actually want to use the lanes or not, 283 * think that the lanes actually are disabled. 291 * If we're asked to disable all lanes, just pretend we're doing 298 * Enable the lanes SRDS_LPD_B [all...] |
H A D | t2080_serdes.c | 16 u8 lanes[SRDS_MAX_LANES]; 195 return ptr->lanes[lane]; 220 if (ptr->lanes[i] != NONE) 15 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
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/u-boot/test/dm/ |
H A D | dsi_host.c | 27 u32 lanes, 26 dm_test_dsi_host_phy_get_lane_mbps(void *priv_data, struct display_timing *timings, u32 lanes, u32 format, unsigned int *lane_mbps) argument
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/u-boot/drivers/phy/rockchip/ |
H A D | phy-rockchip-snps-pcie3.c | 48 * @lanes: The lane to controller mapping 57 u32 lanes[4]; 75 if (priv->lanes[i] > 1) 120 if (!priv->lanes[i]) 123 if (priv->lanes[i] > 1) 222 ret = dev_read_size(dev, "data-lanes"); 226 priv->num_lanes > ARRAY_SIZE(priv->lanes)) { 227 dev_err(dev, "unsupported data-lanes property size\n"); 231 ret = dev_read_u32_array(dev, "data-lanes", priv->lanes, 58 u32 lanes[4]; member in struct:rockchip_p3phy_priv [all...] |
/u-boot/arch/arm/mach-tegra/ |
H A D | xusb-padctl-common.h | 62 const struct tegra_xusb_padctl_lane *lanes; member in struct:tegra_xusb_padctl_soc
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H A D | xusb-padctl-common.c | 69 if (strcmp(name, padctl->socdata->lanes[i].name) == 0) 70 return &padctl->socdata->lanes[i]; 85 len = ofnode_read_string_count(node, "nvidia,lanes"); 87 pr_err("failed to parse \"nvidia,lanes\" property\n"); 94 ret = ofnode_read_string_index(node, "nvidia,lanes", i, 97 pr_err("failed to read string from \"nvidia,lanes\" property\n");
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/u-boot/drivers/video/bridge/ |
H A D | anx6345.c | 271 u8 chipid, colordepth, lanes, data_rate, c; 323 /* Power up and configure lanes */ 358 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) { 362 lanes &= DP_MAX_LANE_COUNT_MASK; 363 debug("%s: lanes: %d\n", __func__, (int)lanes); 365 /* Set data-rate / lanes */ 367 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes); 272 u8 chipid, colordepth, lanes, data_rate, c; local
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H A D | ssd2825.c | 319 pclk_mult = pd_lines / device->lanes + 1; 372 device->lanes - 1); 476 device->lanes = mipi_plat->lanes;
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/u-boot/drivers/pci/ |
H A D | pci_tegra.c | 377 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes, 382 switch (lanes) { 395 switch (lanes) { 414 switch (lanes) { 427 switch (lanes) { 451 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) 456 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1); 458 pr_err("failed to parse \"nvidia,num-lanes\" property\n"); 462 *lanes = err; 484 u32 lanes 378 tegra_pcie_get_xbar_config(ofnode node, u32 lanes, enum tegra_pci_id id, unsigned long *xbar) argument 452 tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) argument 485 u32 lanes = 0; local [all...] |
/u-boot/drivers/video/stm32/ |
H A D | stm32_dsi.c | 265 u32 lanes, u32 format, unsigned int *lane_mbps) argument 286 pll_out_khz = (timings->pixelclock.typ / 1000) * bpp / lanes; 357 device->lanes = mplat->lanes;
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