Searched refs:lanes (Results 1 - 25 of 51) sorted by relevance

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/u-boot/drivers/video/
H A Danx9804.h19 void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp);
21 static inline void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, argument
H A Danx9804.c24 * @lanes: Number of displayport lanes to use
28 void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp)
89 /* Power up and configure lanes */
107 /* Set data-rate / lanes */
109 dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes);
29 anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp) argument
H A Dsamsung-ltl106hl02.c130 plat->lanes = 4;
H A Dtdo-tl070wsh30.c126 plat->lanes = 4;
/u-boot/include/
H A Dphy-mipi-dphy.h270 * @lanes:
272 * Number of active, consecutive, data lanes, starting from
275 unsigned char lanes; member in struct:phy_configure_opts_mipi_dphy
280 unsigned int lanes,
H A Dmipi_dsi.h122 u32 lanes, u32 format, unsigned int *lane_mbps);
199 * @lanes: number of active data lanes
208 unsigned int lanes; member in struct:mipi_dsi_device
241 * @lanes: number of active data lanes
247 unsigned int lanes; member in struct:mipi_dsi_panel_plat
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dls1012a_serdes.c12 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
42 return ptr->lanes[lane];
68 if (ptr->lanes[i] != NONE)
H A Dls1043a_serdes.c12 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
54 return ptr->lanes[lane];
80 if (ptr->lanes[i] != NONE)
H A Dls1028a_serdes.c12 u8 lanes[SRDS_MAX_LANES];
60 return ptr->lanes[lane];
86 if (ptr->lanes[i] != NONE)
11 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
H A Dls1046a_serdes.c13 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
69 return ptr->lanes[lane];
95 if (ptr->lanes[i] != NONE)
H A Dls1088a_serdes.c13 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
113 return ptr->lanes[lane];
139 if (ptr->lanes[i] != NONE)
H A Dlx2160a_serdes.c11 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
118 return ptr->lanes[lane];
144 if (ptr->lanes[i] != NONE)
H A Dls2080a_serdes.c11 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
92 return ptr->lanes[lane];
118 if (ptr->lanes[i] != NONE)
/u-boot/drivers/phy/
H A Dphy-core-mipi-dphy.c20 unsigned int lanes,
30 do_div(hs_clk_rate, lanes);
72 cfg->lanes = lanes;
18 phy_mipi_dphy_get_default_config(unsigned long pixel_clock, unsigned int bpp, unsigned int lanes, struct phy_configure_opts_mipi_dphy *cfg) argument
/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dc29x_serdes.c18 u8 lanes[SRDS1_MAX_LANES];
64 enum srds_prtcl lane_prtcl = ptr->lanes[lane];
19 u8 lanes[SRDS1_MAX_LANES]; member in struct:serdes_config
H A Dfsl_corenet_serdes.c67 } lanes[SRDS_MAX_LANES] = { variable in typeref:struct:__anon85
101 return lanes[lane].idx;
106 return lanes[lane].bank;
114 int bank = lanes[lane].bank;
115 int word = lanes[lane].lpd / 32;
116 int bit = lanes[lane].lpd % 32;
278 * want to enable the bank, whether we actually want to use the lanes or not,
283 * think that the lanes actually are disabled.
291 * If we're asked to disable all lanes, just pretend we're doing
298 * Enable the lanes SRDS_LPD_B
[all...]
H A Dt2080_serdes.c16 u8 lanes[SRDS_MAX_LANES];
195 return ptr->lanes[lane];
220 if (ptr->lanes[i] != NONE)
15 u8 lanes[SRDS_MAX_LANES]; member in struct:serdes_config
/u-boot/test/dm/
H A Ddsi_host.c27 u32 lanes,
26 dm_test_dsi_host_phy_get_lane_mbps(void *priv_data, struct display_timing *timings, u32 lanes, u32 format, unsigned int *lane_mbps) argument
/u-boot/drivers/phy/rockchip/
H A Dphy-rockchip-snps-pcie3.c48 * @lanes: The lane to controller mapping
57 u32 lanes[4];
75 if (priv->lanes[i] > 1)
120 if (!priv->lanes[i])
123 if (priv->lanes[i] > 1)
222 ret = dev_read_size(dev, "data-lanes");
226 priv->num_lanes > ARRAY_SIZE(priv->lanes)) {
227 dev_err(dev, "unsupported data-lanes property size\n");
231 ret = dev_read_u32_array(dev, "data-lanes", priv->lanes,
58 u32 lanes[4]; member in struct:rockchip_p3phy_priv
[all...]
/u-boot/arch/arm/mach-tegra/
H A Dxusb-padctl-common.h62 const struct tegra_xusb_padctl_lane *lanes; member in struct:tegra_xusb_padctl_soc
H A Dxusb-padctl-common.c69 if (strcmp(name, padctl->socdata->lanes[i].name) == 0)
70 return &padctl->socdata->lanes[i];
85 len = ofnode_read_string_count(node, "nvidia,lanes");
87 pr_err("failed to parse \"nvidia,lanes\" property\n");
94 ret = ofnode_read_string_index(node, "nvidia,lanes", i,
97 pr_err("failed to read string from \"nvidia,lanes\" property\n");
/u-boot/drivers/video/bridge/
H A Danx6345.c271 u8 chipid, colordepth, lanes, data_rate, c;
323 /* Power up and configure lanes */
358 if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) {
362 lanes &= DP_MAX_LANE_COUNT_MASK;
363 debug("%s: lanes: %d\n", __func__, (int)lanes);
365 /* Set data-rate / lanes */
367 anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);
272 u8 chipid, colordepth, lanes, data_rate, c; local
H A Dssd2825.c319 pclk_mult = pd_lines / device->lanes + 1;
372 device->lanes - 1);
476 device->lanes = mipi_plat->lanes;
/u-boot/drivers/pci/
H A Dpci_tegra.c377 static int tegra_pcie_get_xbar_config(ofnode node, u32 lanes,
382 switch (lanes) {
395 switch (lanes) {
414 switch (lanes) {
427 switch (lanes) {
451 static int tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes)
456 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1);
458 pr_err("failed to parse \"nvidia,num-lanes\" property\n");
462 *lanes = err;
484 u32 lanes
378 tegra_pcie_get_xbar_config(ofnode node, u32 lanes, enum tegra_pci_id id, unsigned long *xbar) argument
452 tegra_pcie_parse_port_info(ofnode node, uint *index, uint *lanes) argument
485 u32 lanes = 0; local
[all...]
/u-boot/drivers/video/stm32/
H A Dstm32_dsi.c265 u32 lanes, u32 format, unsigned int *lane_mbps) argument
286 pll_out_khz = (timings->pixelclock.typ / 1000) * bpp / lanes;
357 device->lanes = mplat->lanes;

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