1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com> 4 */ 5 6#include <common.h> 7#include <clk.h> 8#include <dm.h> 9#include <log.h> 10#include <misc.h> 11#include <mipi_display.h> 12#include <mipi_dsi.h> 13#include <backlight.h> 14#include <panel.h> 15#include <spi.h> 16#include <linux/delay.h> 17#include <linux/err.h> 18#include <asm/gpio.h> 19 20#define SSD2825_DEVICE_ID_REG 0xB0 21#define SSD2825_RGB_INTERFACE_CTRL_REG_1 0xB1 22#define SSD2825_RGB_INTERFACE_CTRL_REG_2 0xB2 23#define SSD2825_RGB_INTERFACE_CTRL_REG_3 0xB3 24#define SSD2825_RGB_INTERFACE_CTRL_REG_4 0xB4 25#define SSD2825_RGB_INTERFACE_CTRL_REG_5 0xB5 26#define SSD2825_RGB_INTERFACE_CTRL_REG_6 0xB6 27#define SSD2825_NON_BURST BIT(2) 28#define SSD2825_BURST BIT(3) 29#define SSD2825_PCKL_HIGH BIT(13) 30#define SSD2825_HSYNC_HIGH BIT(14) 31#define SSD2825_VSYNC_HIGH BIT(15) 32#define SSD2825_CONFIGURATION_REG 0xB7 33#define SSD2825_CONF_REG_HS BIT(0) 34#define SSD2825_CONF_REG_CKE BIT(1) 35#define SSD2825_CONF_REG_SLP BIT(2) 36#define SSD2825_CONF_REG_VEN BIT(3) 37#define SSD2825_CONF_REG_HCLK BIT(4) 38#define SSD2825_CONF_REG_CSS BIT(5) 39#define SSD2825_CONF_REG_DCS BIT(6) 40#define SSD2825_CONF_REG_REN BIT(7) 41#define SSD2825_CONF_REG_ECD BIT(8) 42#define SSD2825_CONF_REG_EOT BIT(9) 43#define SSD2825_CONF_REG_LPE BIT(10) 44#define SSD2825_VC_CTRL_REG 0xB8 45#define SSD2825_PLL_CTRL_REG 0xB9 46#define SSD2825_PLL_CONFIGURATION_REG 0xBA 47#define SSD2825_CLOCK_CTRL_REG 0xBB 48#define SSD2825_PACKET_SIZE_CTRL_REG_1 0xBC 49#define SSD2825_PACKET_SIZE_CTRL_REG_2 0xBD 50#define SSD2825_PACKET_SIZE_CTRL_REG_3 0xBE 51#define SSD2825_PACKET_DROP_REG 0xBF 52#define SSD2825_OPERATION_CTRL_REG 0xC0 53#define SSD2825_MAX_RETURN_SIZE_REG 0xC1 54#define SSD2825_RETURN_DATA_COUNT_REG 0xC2 55#define SSD2825_ACK_RESPONSE_REG 0xC3 56#define SSD2825_LINE_CTRL_REG 0xC4 57#define SSD2825_INTERRUPT_CTRL_REG 0xC5 58#define SSD2825_INTERRUPT_STATUS_REG 0xC6 59#define SSD2825_ERROR_STATUS_REG 0xC7 60#define SSD2825_DATA_FORMAT_REG 0xC8 61#define SSD2825_DELAY_ADJ_REG_1 0xC9 62#define SSD2825_DELAY_ADJ_REG_2 0xCA 63#define SSD2825_DELAY_ADJ_REG_3 0xCB 64#define SSD2825_DELAY_ADJ_REG_4 0xCC 65#define SSD2825_DELAY_ADJ_REG_5 0xCD 66#define SSD2825_DELAY_ADJ_REG_6 0xCE 67#define SSD2825_HS_TX_TIMER_REG_1 0xCF 68#define SSD2825_HS_TX_TIMER_REG_2 0xD0 69#define SSD2825_LP_RX_TIMER_REG_1 0xD1 70#define SSD2825_LP_RX_TIMER_REG_2 0xD2 71#define SSD2825_TE_STATUS_REG 0xD3 72#define SSD2825_SPI_READ_REG 0xD4 73#define SSD2825_PLL_LOCK_REG 0xD5 74#define SSD2825_TEST_REG 0xD6 75#define SSD2825_TE_COUNT_REG 0xD7 76#define SSD2825_ANALOG_CTRL_REG_1 0xD8 77#define SSD2825_ANALOG_CTRL_REG_2 0xD9 78#define SSD2825_ANALOG_CTRL_REG_3 0xDA 79#define SSD2825_ANALOG_CTRL_REG_4 0xDB 80#define SSD2825_INTERRUPT_OUT_CTRL_REG 0xDC 81#define SSD2825_RGB_INTERFACE_CTRL_REG_7 0xDD 82#define SSD2825_LANE_CONFIGURATION_REG 0xDE 83#define SSD2825_DELAY_ADJ_REG_7 0xDF 84#define SSD2825_INPUT_PIN_CTRL_REG_1 0xE0 85#define SSD2825_INPUT_PIN_CTRL_REG_2 0xE1 86#define SSD2825_BIDIR_PIN_CTRL_REG_1 0xE2 87#define SSD2825_BIDIR_PIN_CTRL_REG_2 0xE3 88#define SSD2825_BIDIR_PIN_CTRL_REG_3 0xE4 89#define SSD2825_BIDIR_PIN_CTRL_REG_4 0xE5 90#define SSD2825_BIDIR_PIN_CTRL_REG_5 0xE6 91#define SSD2825_BIDIR_PIN_CTRL_REG_6 0xE7 92#define SSD2825_BIDIR_PIN_CTRL_REG_7 0xE8 93#define SSD2825_CABC_BRIGHTNESS_CTRL_REG_1 0xE9 94#define SSD2825_CABC_BRIGHTNESS_CTRL_REG_2 0xEA 95#define SSD2825_CABC_BRIGHTNESS_STATUS_REG 0xEB 96#define SSD2825_READ_REG 0xFF 97#define SSD2825_SPI_READ_REG_RESET 0xFA 98 99#define SSD2825_CMD_MASK 0x00 100#define SSD2825_DAT_MASK 0x01 101 102#define SSD2825_CMD_SEND BIT(0) 103#define SSD2825_DAT_SEND BIT(1) 104#define SSD2825_DSI_SEND BIT(2) 105 106#define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3F) 107#define SSD2825_LP_MIN_CLK 5000 /* KHz */ 108#define SSD2825_REF_MIN_CLK 2000 /* KHz */ 109 110struct ssd2825_bridge_priv { 111 struct mipi_dsi_host host; 112 struct mipi_dsi_device device; 113 114 struct udevice *panel; 115 struct display_timing timing; 116 117 struct gpio_desc power_gpio; 118 struct gpio_desc reset_gpio; 119 120 struct clk *tx_clk; 121 122 u32 pll_freq_kbps; /* PLL in kbps */ 123}; 124 125static int ssd2825_spi_write(struct udevice *dev, int reg, 126 const void *buf, int flags) 127{ 128 u8 command[2]; 129 130 if (flags & SSD2825_CMD_SEND) { 131 command[0] = SSD2825_CMD_MASK; 132 command[1] = reg; 133 dm_spi_xfer(dev, 9, &command, 134 NULL, SPI_XFER_ONCE); 135 } 136 137 if (flags & SSD2825_DAT_SEND) { 138 u16 data = *(u16 *)buf; 139 u8 cmd1, cmd2; 140 141 /* send low byte first and then high byte */ 142 cmd1 = (data & 0x00FF); 143 cmd2 = (data & 0xFF00) >> 8; 144 145 command[0] = SSD2825_DAT_MASK; 146 command[1] = cmd1; 147 dm_spi_xfer(dev, 9, &command, 148 NULL, SPI_XFER_ONCE); 149 150 command[0] = SSD2825_DAT_MASK; 151 command[1] = cmd2; 152 dm_spi_xfer(dev, 9, &command, 153 NULL, SPI_XFER_ONCE); 154 } 155 156 if (flags & SSD2825_DSI_SEND) { 157 u16 data = *(u16 *)buf; 158 data &= 0x00FF; 159 160 debug("%s: dsi command (0x%x)\n", 161 __func__, data); 162 163 command[0] = SSD2825_DAT_MASK; 164 command[1] = data; 165 dm_spi_xfer(dev, 9, &command, 166 NULL, SPI_XFER_ONCE); 167 } 168 169 return 0; 170} 171 172static int ssd2825_spi_read(struct udevice *dev, int reg, 173 void *data, int flags) 174{ 175 u8 command[2]; 176 177 command[0] = SSD2825_CMD_MASK; 178 command[1] = SSD2825_SPI_READ_REG; 179 dm_spi_xfer(dev, 9, &command, 180 NULL, SPI_XFER_ONCE); 181 182 command[0] = SSD2825_DAT_MASK; 183 command[1] = SSD2825_SPI_READ_REG_RESET; 184 dm_spi_xfer(dev, 9, &command, 185 NULL, SPI_XFER_ONCE); 186 187 command[0] = SSD2825_DAT_MASK; 188 command[1] = 0; 189 dm_spi_xfer(dev, 9, &command, 190 NULL, SPI_XFER_ONCE); 191 192 command[0] = SSD2825_CMD_MASK; 193 command[1] = reg; 194 dm_spi_xfer(dev, 9, &command, 195 NULL, SPI_XFER_ONCE); 196 197 command[0] = SSD2825_CMD_MASK; 198 command[1] = SSD2825_SPI_READ_REG_RESET; 199 dm_spi_xfer(dev, 9, &command, 200 NULL, SPI_XFER_ONCE); 201 202 dm_spi_xfer(dev, 16, NULL, 203 (u8 *)data, SPI_XFER_ONCE); 204 205 return 0; 206} 207 208static void ssd2825_write_register(struct udevice *dev, u8 reg, 209 u16 command) 210{ 211 ssd2825_spi_write(dev, reg, &command, 212 SSD2825_CMD_SEND | 213 SSD2825_DAT_SEND); 214} 215 216static void ssd2825_write_dsi(struct udevice *dev, const u8 *command, 217 int len) 218{ 219 int i; 220 221 ssd2825_spi_write(dev, SSD2825_PACKET_SIZE_CTRL_REG_1, &len, 222 SSD2825_CMD_SEND | SSD2825_DAT_SEND); 223 224 ssd2825_spi_write(dev, SSD2825_PACKET_DROP_REG, NULL, 225 SSD2825_CMD_SEND); 226 227 for (i = 0; i < len; i++) 228 ssd2825_spi_write(dev, 0, &command[i], SSD2825_DSI_SEND); 229} 230 231static ssize_t ssd2825_bridge_transfer(struct mipi_dsi_host *host, 232 const struct mipi_dsi_msg *msg) 233{ 234 struct udevice *dev = (struct udevice *)host->dev; 235 u8 buf = *(u8 *)msg->tx_buf; 236 u16 config; 237 int ret; 238 239 ret = ssd2825_spi_read(dev, SSD2825_CONFIGURATION_REG, 240 &config, 0); 241 if (ret) 242 return ret; 243 244 switch (msg->type) { 245 case MIPI_DSI_DCS_SHORT_WRITE: 246 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 247 case MIPI_DSI_DCS_LONG_WRITE: 248 config |= SSD2825_CONF_REG_DCS; 249 break; 250 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 251 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 252 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 253 case MIPI_DSI_GENERIC_LONG_WRITE: 254 config &= ~SSD2825_CONF_REG_DCS; 255 break; 256 default: 257 return 0; 258 } 259 260 ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG, config); 261 ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000); 262 ssd2825_write_dsi(dev, msg->tx_buf, msg->tx_len); 263 264 if (buf == MIPI_DCS_SET_DISPLAY_ON) { 265 ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG, 266 SSD2825_CONF_REG_HS | SSD2825_CONF_REG_VEN | 267 SSD2825_CONF_REG_DCS | SSD2825_CONF_REG_ECD | 268 SSD2825_CONF_REG_EOT); 269 ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001); 270 ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000); 271 } 272 273 return 0; 274} 275 276static const struct mipi_dsi_host_ops ssd2825_bridge_host_ops = { 277 .transfer = ssd2825_bridge_transfer, 278}; 279 280/* 281 * PLL configuration register settings. 282 * 283 * See the "PLL Configuration Register Description" in the SSD2825 datasheet. 284 */ 285static u16 construct_pll_config(struct ssd2825_bridge_priv *priv, 286 u32 desired_pll_freq_kbps, u32 reference_freq_khz) 287{ 288 u32 div_factor = 1, mul_factor, fr = 0; 289 290 while (reference_freq_khz / (div_factor + 1) >= SSD2825_REF_MIN_CLK) 291 div_factor++; 292 if (div_factor > 31) 293 div_factor = 31; 294 295 mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor, 296 reference_freq_khz); 297 298 priv->pll_freq_kbps = reference_freq_khz * mul_factor / div_factor; 299 300 if (priv->pll_freq_kbps >= 501000) 301 fr = 3; 302 else if (priv->pll_freq_kbps >= 251000) 303 fr = 2; 304 else if (priv->pll_freq_kbps >= 126000) 305 fr = 1; 306 307 return (fr << 14) | (div_factor << 8) | mul_factor; 308} 309 310static void ssd2825_setup_pll(struct udevice *dev) 311{ 312 struct ssd2825_bridge_priv *priv = dev_get_priv(dev); 313 struct mipi_dsi_device *device = &priv->device; 314 struct display_timing *dt = &priv->timing; 315 u16 pll_config, lp_div; 316 u32 pclk_mult, tx_freq_khz, pd_lines; 317 318 tx_freq_khz = clk_get_rate(priv->tx_clk) / 1000; 319 pd_lines = mipi_dsi_pixel_format_to_bpp(device->format); 320 pclk_mult = pd_lines / device->lanes + 1; 321 322 pll_config = construct_pll_config(priv, pclk_mult * 323 dt->pixelclock.typ / 1000, 324 tx_freq_khz); 325 326 lp_div = priv->pll_freq_kbps / (SSD2825_LP_MIN_CLK * 8); 327 328 /* Disable PLL */ 329 ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0000); 330 ssd2825_write_register(dev, SSD2825_LINE_CTRL_REG, 0x0001); 331 332 /* Set delays */ 333 ssd2825_write_register(dev, SSD2825_DELAY_ADJ_REG_1, 0x2103); 334 335 /* Set PLL coeficients */ 336 ssd2825_write_register(dev, SSD2825_PLL_CONFIGURATION_REG, pll_config); 337 338 /* Clock Control Register */ 339 ssd2825_write_register(dev, SSD2825_CLOCK_CTRL_REG, 340 SSD2828_LP_CLOCK_DIVIDER(lp_div)); 341 342 /* Enable PLL */ 343 ssd2825_write_register(dev, SSD2825_PLL_CTRL_REG, 0x0001); 344 ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000); 345} 346 347static int ssd2825_bridge_enable_panel(struct udevice *dev) 348{ 349 struct ssd2825_bridge_priv *priv = dev_get_priv(dev); 350 struct mipi_dsi_device *device = &priv->device; 351 struct display_timing *dt = &priv->timing; 352 353 /* Perform SW reset */ 354 ssd2825_write_register(dev, SSD2825_OPERATION_CTRL_REG, 0x0100); 355 356 /* Set panel timings */ 357 ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_1, 358 dt->vsync_len.typ << 8 | dt->hsync_len.typ); 359 ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_2, 360 (dt->vsync_len.typ + dt->vback_porch.typ) << 8 | 361 (dt->hsync_len.typ + dt->hback_porch.typ)); 362 ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_3, 363 dt->vfront_porch.typ << 8 | dt->hfront_porch.typ); 364 ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_4, 365 dt->hactive.typ); 366 ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_5, 367 dt->vactive.typ); 368 ssd2825_write_register(dev, SSD2825_RGB_INTERFACE_CTRL_REG_6, 369 SSD2825_HSYNC_HIGH | SSD2825_VSYNC_HIGH | 370 SSD2825_PCKL_HIGH | SSD2825_NON_BURST | 371 (3 - device->format)); 372 ssd2825_write_register(dev, SSD2825_LANE_CONFIGURATION_REG, 373 device->lanes - 1); 374 ssd2825_write_register(dev, SSD2825_TEST_REG, 0x0004); 375 376 /* Call PLL configuration */ 377 ssd2825_setup_pll(dev); 378 379 mdelay(10); 380 381 /* Initial DSI configuration register set */ 382 ssd2825_write_register(dev, SSD2825_CONFIGURATION_REG, 383 SSD2825_CONF_REG_CKE | SSD2825_CONF_REG_DCS | 384 SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT); 385 ssd2825_write_register(dev, SSD2825_VC_CTRL_REG, 0x0000); 386 387 /* Perform panel setup */ 388 return panel_enable_backlight(priv->panel); 389} 390 391static int ssd2825_bridge_set_panel(struct udevice *dev, int percent) 392{ 393 struct ssd2825_bridge_priv *priv = dev_get_priv(dev); 394 395 return panel_set_backlight(priv->panel, percent); 396} 397 398static int ssd2825_bridge_panel_timings(struct udevice *dev, 399 struct display_timing *timing) 400{ 401 struct ssd2825_bridge_priv *priv = dev_get_priv(dev); 402 403 memcpy(timing, &priv->timing, sizeof(*timing)); 404 405 return 0; 406} 407 408static int ssd2825_bridge_hw_init(struct udevice *dev) 409{ 410 struct ssd2825_bridge_priv *priv = dev_get_priv(dev); 411 int ret; 412 413 ret = clk_prepare_enable(priv->tx_clk); 414 if (ret) { 415 log_debug("%s: error enabling tx_clk (%d)\n", 416 __func__, ret); 417 return ret; 418 } 419 420 ret = dm_gpio_set_value(&priv->power_gpio, 1); 421 if (ret) { 422 log_debug("%s: error changing power-gpios (%d)\n", 423 __func__, ret); 424 return ret; 425 } 426 mdelay(10); 427 428 ret = dm_gpio_set_value(&priv->reset_gpio, 0); 429 if (ret) { 430 log_debug("%s: error changing reset-gpios (%d)\n", 431 __func__, ret); 432 return ret; 433 } 434 mdelay(10); 435 436 ret = dm_gpio_set_value(&priv->reset_gpio, 1); 437 if (ret) { 438 log_debug("%s: error changing reset-gpios (%d)\n", 439 __func__, ret); 440 return ret; 441 } 442 mdelay(10); 443 444 return 0; 445} 446 447static int ssd2825_bridge_probe(struct udevice *dev) 448{ 449 struct ssd2825_bridge_priv *priv = dev_get_priv(dev); 450 struct spi_slave *slave = dev_get_parent_priv(dev); 451 struct mipi_dsi_device *device = &priv->device; 452 struct mipi_dsi_panel_plat *mipi_plat; 453 int ret; 454 455 ret = spi_claim_bus(slave); 456 if (ret) { 457 log_err("SPI bus allocation failed (%d)\n", ret); 458 return ret; 459 } 460 461 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, 462 "panel", &priv->panel); 463 if (ret) { 464 log_err("cannot get panel: ret=%d\n", ret); 465 return ret; 466 } 467 468 panel_get_display_timing(priv->panel, &priv->timing); 469 470 mipi_plat = dev_get_plat(priv->panel); 471 mipi_plat->device = device; 472 473 priv->host.dev = (struct device *)dev; 474 priv->host.ops = &ssd2825_bridge_host_ops; 475 476 device->host = &priv->host; 477 device->lanes = mipi_plat->lanes; 478 device->format = mipi_plat->format; 479 device->mode_flags = mipi_plat->mode_flags; 480 481 /* get panel gpios */ 482 ret = gpio_request_by_name(dev, "power-gpios", 0, 483 &priv->power_gpio, GPIOD_IS_OUT); 484 if (ret) { 485 log_err("could not decode power-gpios (%d)\n", ret); 486 return ret; 487 } 488 489 ret = gpio_request_by_name(dev, "reset-gpios", 0, 490 &priv->reset_gpio, GPIOD_IS_OUT); 491 if (ret) { 492 log_err("could not decode reset-gpios (%d)\n", ret); 493 return ret; 494 } 495 496 /* get clk */ 497 priv->tx_clk = devm_clk_get(dev, "tx_clk"); 498 if (IS_ERR(priv->tx_clk)) { 499 log_err("cannot get tx_clk: %ld\n", PTR_ERR(priv->tx_clk)); 500 return PTR_ERR(priv->tx_clk); 501 } 502 503 return ssd2825_bridge_hw_init(dev); 504} 505 506static const struct panel_ops ssd2825_bridge_ops = { 507 .enable_backlight = ssd2825_bridge_enable_panel, 508 .set_backlight = ssd2825_bridge_set_panel, 509 .get_display_timing = ssd2825_bridge_panel_timings, 510}; 511 512static const struct udevice_id ssd2825_bridge_ids[] = { 513 { .compatible = "solomon,ssd2825" }, 514 { } 515}; 516 517U_BOOT_DRIVER(ssd2825) = { 518 .name = "ssd2825", 519 .id = UCLASS_PANEL, 520 .of_match = ssd2825_bridge_ids, 521 .ops = &ssd2825_bridge_ops, 522 .probe = ssd2825_bridge_probe, 523 .priv_auto = sizeof(struct ssd2825_bridge_priv), 524}; 525