1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2019 STMicroelectronics - All Rights Reserved 4 * Author(s): Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics. 5 * Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics. 6 * 7 * This MIPI DSI controller driver is based on the Linux Kernel driver from 8 * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c. 9 */ 10 11#define LOG_CATEGORY UCLASS_VIDEO_BRIDGE 12 13#include <common.h> 14#include <clk.h> 15#include <dm.h> 16#include <dsi_host.h> 17#include <log.h> 18#include <mipi_dsi.h> 19#include <panel.h> 20#include <reset.h> 21#include <video.h> 22#include <video_bridge.h> 23#include <asm/io.h> 24#include <dm/device-internal.h> 25#include <dm/device_compat.h> 26#include <dm/lists.h> 27#include <linux/bitops.h> 28#include <linux/iopoll.h> 29#include <linux/printk.h> 30#include <power/regulator.h> 31 32#define HWVER_130 0x31333000 /* IP version 1.30 */ 33#define HWVER_131 0x31333100 /* IP version 1.31 */ 34 35/* DSI digital registers & bit definitions */ 36#define DSI_VERSION 0x00 37#define VERSION GENMASK(31, 8) 38 39/* 40 * DSI wrapper registers & bit definitions 41 * Note: registers are named as in the Reference Manual 42 */ 43#define DSI_WCFGR 0x0400 /* Wrapper ConFiGuration Reg */ 44#define WCFGR_DSIM BIT(0) /* DSI Mode */ 45#define WCFGR_COLMUX GENMASK(3, 1) /* COLor MUltipleXing */ 46 47#define DSI_WCR 0x0404 /* Wrapper Control Reg */ 48#define WCR_DSIEN BIT(3) /* DSI ENable */ 49 50#define DSI_WISR 0x040C /* Wrapper Interrupt and Status Reg */ 51#define WISR_PLLLS BIT(8) /* PLL Lock Status */ 52#define WISR_RRS BIT(12) /* Regulator Ready Status */ 53 54#define DSI_WPCR0 0x0418 /* Wrapper Phy Conf Reg 0 */ 55#define WPCR0_UIX4 GENMASK(5, 0) /* Unit Interval X 4 */ 56#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */ 57 58#define DSI_WRPCR 0x0430 /* Wrapper Regulator & Pll Ctrl Reg */ 59#define WRPCR_PLLEN BIT(0) /* PLL ENable */ 60#define WRPCR_NDIV GENMASK(8, 2) /* pll loop DIVision Factor */ 61#define WRPCR_IDF GENMASK(14, 11) /* pll Input Division Factor */ 62#define WRPCR_ODF GENMASK(17, 16) /* pll Output Division Factor */ 63#define WRPCR_REGEN BIT(24) /* REGulator ENable */ 64#define WRPCR_BGREN BIT(28) /* BandGap Reference ENable */ 65#define IDF_MIN 1 66#define IDF_MAX 7 67#define NDIV_MIN 10 68#define NDIV_MAX 125 69#define ODF_MIN 1 70#define ODF_MAX 8 71 72/* dsi color format coding according to the datasheet */ 73enum dsi_color { 74 DSI_RGB565_CONF1, 75 DSI_RGB565_CONF2, 76 DSI_RGB565_CONF3, 77 DSI_RGB666_CONF1, 78 DSI_RGB666_CONF2, 79 DSI_RGB888, 80}; 81 82#define LANE_MIN_KBPS 31250 83#define LANE_MAX_KBPS 500000 84 85/* Timeout for regulator on/off, pll lock/unlock & fifo empty */ 86#define TIMEOUT_US 200000 87 88struct stm32_dsi_priv { 89 struct mipi_dsi_device device; 90 void __iomem *base; 91 struct udevice *panel; 92 u32 pllref_clk; 93 u32 hw_version; 94 int lane_min_kbps; 95 int lane_max_kbps; 96 struct udevice *vdd_reg; 97 struct udevice *dsi_host; 98}; 99 100static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val) 101{ 102 writel(val, dsi->base + reg); 103} 104 105static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg) 106{ 107 return readl(dsi->base + reg); 108} 109 110static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask) 111{ 112 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); 113} 114 115static inline void dsi_clear(struct stm32_dsi_priv *dsi, u32 reg, u32 mask) 116{ 117 dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask); 118} 119 120static inline void dsi_update_bits(struct stm32_dsi_priv *dsi, u32 reg, 121 u32 mask, u32 val) 122{ 123 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); 124} 125 126static enum dsi_color dsi_color_from_mipi(u32 fmt) 127{ 128 switch (fmt) { 129 case MIPI_DSI_FMT_RGB888: 130 return DSI_RGB888; 131 case MIPI_DSI_FMT_RGB666: 132 return DSI_RGB666_CONF2; 133 case MIPI_DSI_FMT_RGB666_PACKED: 134 return DSI_RGB666_CONF1; 135 case MIPI_DSI_FMT_RGB565: 136 return DSI_RGB565_CONF1; 137 default: 138 log_err("MIPI color invalid, so we use rgb888\n"); 139 } 140 return DSI_RGB888; 141} 142 143static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf) 144{ 145 int divisor = idf * odf; 146 147 /* prevent from division by 0 */ 148 if (!divisor) 149 return 0; 150 151 return DIV_ROUND_CLOSEST(clkin_khz * ndiv, divisor); 152} 153 154static int dsi_pll_get_params(struct stm32_dsi_priv *dsi, 155 int clkin_khz, int clkout_khz, 156 int *idf, int *ndiv, int *odf) 157{ 158 int i, o, n, n_min, n_max; 159 int fvco_min, fvco_max, delta, best_delta; /* all in khz */ 160 161 /* Early checks preventing division by 0 & odd results */ 162 if (clkin_khz <= 0 || clkout_khz <= 0) 163 return -EINVAL; 164 165 fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX; 166 fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN; 167 168 best_delta = 1000000; /* big started value (1000000khz) */ 169 170 for (i = IDF_MIN; i <= IDF_MAX; i++) { 171 /* Compute ndiv range according to Fvco */ 172 n_min = ((fvco_min * i) / (2 * clkin_khz)) + 1; 173 n_max = (fvco_max * i) / (2 * clkin_khz); 174 175 /* No need to continue idf loop if we reach ndiv max */ 176 if (n_min >= NDIV_MAX) 177 break; 178 179 /* Clamp ndiv to valid values */ 180 if (n_min < NDIV_MIN) 181 n_min = NDIV_MIN; 182 if (n_max > NDIV_MAX) 183 n_max = NDIV_MAX; 184 185 for (o = ODF_MIN; o <= ODF_MAX; o *= 2) { 186 n = DIV_ROUND_CLOSEST(i * o * clkout_khz, clkin_khz); 187 /* Check ndiv according to vco range */ 188 if (n < n_min || n > n_max) 189 continue; 190 /* Check if new delta is better & saves parameters */ 191 delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) - 192 clkout_khz; 193 if (delta < 0) 194 delta = -delta; 195 if (delta < best_delta) { 196 *idf = i; 197 *ndiv = n; 198 *odf = o; 199 best_delta = delta; 200 } 201 /* fast return in case of "perfect result" */ 202 if (!delta) 203 return 0; 204 } 205 } 206 207 return 0; 208} 209 210static int dsi_phy_init(void *priv_data) 211{ 212 struct mipi_dsi_device *device = priv_data; 213 struct udevice *dev = device->dev; 214 struct stm32_dsi_priv *dsi = dev_get_priv(dev); 215 u32 val; 216 int ret; 217 218 dev_dbg(dev, "Initialize DSI physical layer\n"); 219 220 /* Enable the regulator */ 221 dsi_set(dsi, DSI_WRPCR, WRPCR_REGEN | WRPCR_BGREN); 222 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS, 223 TIMEOUT_US); 224 if (ret) { 225 dev_dbg(dev, "!TIMEOUT! waiting REGU\n"); 226 return ret; 227 } 228 229 /* Enable the DSI PLL & wait for its lock */ 230 dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN); 231 ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS, 232 TIMEOUT_US); 233 if (ret) { 234 dev_dbg(dev, "!TIMEOUT! waiting PLL\n"); 235 return ret; 236 } 237 238 return 0; 239} 240 241static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags) 242{ 243 struct mipi_dsi_device *device = priv_data; 244 struct udevice *dev = device->dev; 245 struct stm32_dsi_priv *dsi = dev_get_priv(dev); 246 247 dev_dbg(dev, "Set mode %p enable %ld\n", dsi, 248 mode_flags & MIPI_DSI_MODE_VIDEO); 249 250 if (!dsi) 251 return; 252 253 /* 254 * DSI wrapper must be enabled in video mode & disabled in command mode. 255 * If wrapper is enabled in command mode, the display controller 256 * register access will hang. 257 */ 258 259 if (mode_flags & MIPI_DSI_MODE_VIDEO) 260 dsi_set(dsi, DSI_WCR, WCR_DSIEN); 261 else 262 dsi_clear(dsi, DSI_WCR, WCR_DSIEN); 263} 264 265static int dsi_get_lane_mbps(void *priv_data, struct display_timing *timings, 266 u32 lanes, u32 format, unsigned int *lane_mbps) 267{ 268 struct mipi_dsi_device *device = priv_data; 269 struct udevice *dev = device->dev; 270 struct stm32_dsi_priv *dsi = dev_get_priv(dev); 271 int idf, ndiv, odf, pll_in_khz, pll_out_khz; 272 int ret, bpp; 273 u32 val; 274 275 /* Update lane capabilities according to hw version */ 276 dsi->lane_min_kbps = LANE_MIN_KBPS; 277 dsi->lane_max_kbps = LANE_MAX_KBPS; 278 if (dsi->hw_version == HWVER_131) { 279 dsi->lane_min_kbps *= 2; 280 dsi->lane_max_kbps *= 2; 281 } 282 283 pll_in_khz = dsi->pllref_clk / 1000; 284 285 /* Compute requested pll out */ 286 bpp = mipi_dsi_pixel_format_to_bpp(format); 287 pll_out_khz = (timings->pixelclock.typ / 1000) * bpp / lanes; 288 /* Add 20% to pll out to be higher than pixel bw (burst mode only) */ 289 pll_out_khz = (pll_out_khz * 12) / 10; 290 if (pll_out_khz > dsi->lane_max_kbps) { 291 pll_out_khz = dsi->lane_max_kbps; 292 dev_warn(dev, "Warning max phy mbps is used\n"); 293 } 294 if (pll_out_khz < dsi->lane_min_kbps) { 295 pll_out_khz = dsi->lane_min_kbps; 296 dev_warn(dev, "Warning min phy mbps is used\n"); 297 } 298 299 /* Compute best pll parameters */ 300 idf = 0; 301 ndiv = 0; 302 odf = 0; 303 ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz, 304 &idf, &ndiv, &odf); 305 if (ret) { 306 dev_err(dev, "Warning dsi_pll_get_params(): bad params\n"); 307 return ret; 308 } 309 310 /* Get the adjusted pll out value */ 311 pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); 312 313 /* Set the PLL division factors */ 314 dsi_update_bits(dsi, DSI_WRPCR, WRPCR_NDIV | WRPCR_IDF | WRPCR_ODF, 315 (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); 316 317 /* Compute uix4 & set the bit period in high-speed mode */ 318 val = 4000000 / pll_out_khz; 319 dsi_update_bits(dsi, DSI_WPCR0, WPCR0_UIX4, val); 320 321 /* Select video mode by resetting DSIM bit */ 322 dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM); 323 324 /* Select the color coding */ 325 dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX, 326 dsi_color_from_mipi(format) << 1); 327 328 *lane_mbps = pll_out_khz / 1000; 329 330 dev_dbg(dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", 331 pll_in_khz, pll_out_khz, *lane_mbps); 332 333 return 0; 334} 335 336static const struct mipi_dsi_phy_ops dsi_stm_phy_ops = { 337 .init = dsi_phy_init, 338 .get_lane_mbps = dsi_get_lane_mbps, 339 .post_set_mode = dsi_phy_post_set_mode, 340}; 341 342static int stm32_dsi_attach(struct udevice *dev) 343{ 344 struct stm32_dsi_priv *priv = dev_get_priv(dev); 345 struct mipi_dsi_device *device = &priv->device; 346 struct mipi_dsi_panel_plat *mplat; 347 struct display_timing timings; 348 int ret; 349 350 ret = uclass_first_device_err(UCLASS_PANEL, &priv->panel); 351 if (ret) { 352 dev_err(dev, "panel device error %d\n", ret); 353 return ret; 354 } 355 356 mplat = dev_get_plat(priv->panel); 357 mplat->device = &priv->device; 358 device->lanes = mplat->lanes; 359 device->format = mplat->format; 360 device->mode_flags = mplat->mode_flags; 361 362 ret = panel_get_display_timing(priv->panel, &timings); 363 if (ret) { 364 ret = ofnode_decode_display_timing(dev_ofnode(priv->panel), 365 0, &timings); 366 if (ret) { 367 dev_err(dev, "decode display timing error %d\n", ret); 368 return ret; 369 } 370 } 371 372 ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host); 373 if (ret) { 374 dev_err(dev, "No video dsi host detected %d\n", ret); 375 return ret; 376 } 377 378 ret = dsi_host_init(priv->dsi_host, device, &timings, 2, 379 &dsi_stm_phy_ops); 380 if (ret) { 381 dev_err(dev, "failed to initialize mipi dsi host\n"); 382 return ret; 383 } 384 385 return 0; 386} 387 388static int stm32_dsi_set_backlight(struct udevice *dev, int percent) 389{ 390 struct stm32_dsi_priv *priv = dev_get_priv(dev); 391 int ret; 392 393 ret = panel_enable_backlight(priv->panel); 394 if (ret) { 395 dev_err(dev, "panel %s enable backlight error %d\n", 396 priv->panel->name, ret); 397 return ret; 398 } 399 400 ret = dsi_host_enable(priv->dsi_host); 401 if (ret) { 402 dev_err(dev, "failed to enable mipi dsi host\n"); 403 return ret; 404 } 405 406 return 0; 407} 408 409static int stm32_dsi_bind(struct udevice *dev) 410{ 411 int ret; 412 413 ret = device_bind_driver_to_node(dev, "dw_mipi_dsi", "dsihost", 414 dev_ofnode(dev), NULL); 415 if (ret) 416 return ret; 417 418 return dm_scan_fdt_dev(dev); 419} 420 421static int stm32_dsi_probe(struct udevice *dev) 422{ 423 struct stm32_dsi_priv *priv = dev_get_priv(dev); 424 struct mipi_dsi_device *device = &priv->device; 425 struct reset_ctl rst; 426 struct clk clk; 427 int ret; 428 429 device->dev = dev; 430 431 priv->base = dev_read_addr_ptr(dev); 432 if (!priv->base) { 433 dev_err(dev, "dsi dt register address error\n"); 434 return -EINVAL; 435 } 436 437 ret = device_get_supply_regulator(dev, "phy-dsi-supply", 438 &priv->vdd_reg); 439 if (ret && ret != -ENOENT) { 440 dev_err(dev, "Warning: cannot get phy dsi supply\n"); 441 return -ENODEV; 442 } 443 444 if (ret != -ENOENT) { 445 ret = regulator_set_enable(priv->vdd_reg, true); 446 if (ret) 447 return ret; 448 } 449 450 ret = clk_get_by_name(device->dev, "pclk", &clk); 451 if (ret) { 452 dev_err(dev, "peripheral clock get error %d\n", ret); 453 goto err_reg; 454 } 455 456 ret = clk_enable(&clk); 457 if (ret) { 458 dev_err(dev, "peripheral clock enable error %d\n", ret); 459 goto err_reg; 460 } 461 462 ret = clk_get_by_name(dev, "ref", &clk); 463 if (ret) { 464 dev_err(dev, "pll reference clock get error %d\n", ret); 465 goto err_clk; 466 } 467 468 priv->pllref_clk = (unsigned int)clk_get_rate(&clk); 469 470 ret = reset_get_by_index(device->dev, 0, &rst); 471 if (ret) { 472 dev_err(dev, "missing dsi hardware reset\n"); 473 goto err_clk; 474 } 475 476 /* Reset */ 477 reset_deassert(&rst); 478 479 /* check hardware version */ 480 priv->hw_version = dsi_read(priv, DSI_VERSION) & VERSION; 481 if (priv->hw_version != HWVER_130 && 482 priv->hw_version != HWVER_131) { 483 dev_err(dev, "DSI version 0x%x not supported\n", priv->hw_version); 484 dev_dbg(dev, "remove and unbind all DSI child\n"); 485 device_chld_remove(dev, NULL, DM_REMOVE_NORMAL); 486 device_chld_unbind(dev, NULL); 487 ret = -ENODEV; 488 goto err_clk; 489 } 490 491 return 0; 492err_clk: 493 clk_disable(&clk); 494err_reg: 495 regulator_set_enable(priv->vdd_reg, false); 496 497 return ret; 498} 499 500struct video_bridge_ops stm32_dsi_ops = { 501 .attach = stm32_dsi_attach, 502 .set_backlight = stm32_dsi_set_backlight, 503}; 504 505static const struct udevice_id stm32_dsi_ids[] = { 506 { .compatible = "st,stm32-dsi"}, 507 { } 508}; 509 510U_BOOT_DRIVER(stm32_dsi) = { 511 .name = "stm32-display-dsi", 512 .id = UCLASS_VIDEO_BRIDGE, 513 .of_match = stm32_dsi_ids, 514 .bind = stm32_dsi_bind, 515 .probe = stm32_dsi_probe, 516 .ops = &stm32_dsi_ops, 517 .priv_auto = sizeof(struct stm32_dsi_priv), 518}; 519