#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
935b60f8 |
|
30-Apr-2024 |
Tom Rini <trini@konsulko.com> |
arm: fsl-layerscape: Remove <common.h> and add needed includes Remove <common.h> from all fsl-layerscape related files and when needed add missing include files directly. Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
430a5542 |
|
10-Jan-2020 |
Alex Marginean <alexandru.marginean@nxp.com> |
armv8: ls1028a_serdes: Add few missing serdes protocols Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
116f75c7 |
|
04-Sep-2019 |
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> |
armv8: ls1028a: Updated serdes configuration for 0x13BB In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b75238e ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
|
#
36f50b75 |
|
21-May-2019 |
Xiaowei Bao <xiaowei.bao@nxp.com> |
armv8: ls1028a: Add other serdes protocal support Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|
#
d4ad111d |
|
10-Apr-2019 |
Yuantian Tang <andy.tang@nxp.com> |
armv8: ls1028a: Add NXP LS1028A SoC support Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
|