| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 153 * @input_rate: Input clock rate in Hz
157 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) argument
161 clk_div = input_rate / output_rate;
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| /u-boot/drivers/clk/aspeed/ |
| H A D | clk_ast2500.c | 208 ulong input_rate; member in struct:ast2500_clock_config
217 static bool ast2500_get_clock_config_default(ulong input_rate, argument
226 if (default_cfg->input_rate == input_rate &&
237 * @input_rate - the rate of input clock in Hz
246 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, argument
253 const ulong input_rate_khz = input_rate / 1000;
263 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
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| /u-boot/drivers/spi/ |
| H A D | rk_spi.c | 61 uint input_rate; member in struct:rockchip_spi_priv
96 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
108 __func__, speed, priv->input_rate / clk_div);
281 priv->input_rate = ret;
282 debug("%s: rate = %u\n", __func__, priv->input_rate);
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| /u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 30 #define RATE_TO_DIV(input_rate, output_rate) \
31 ((input_rate) / (output_rate) - 1);
33 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3328.c | 32 #define RATE_TO_DIV(input_rate, output_rate) \
33 ((input_rate) / (output_rate) - 1);
34 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk322x.c | 31 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3128.c | 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3066.c | 72 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3188.c | 75 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3368.c | 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rv1108.c | 34 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3399.c | 48 #define RATE_TO_DIV(input_rate, output_rate) \
49 ((input_rate) / (output_rate) - 1)
50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3288.c | 137 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3308.c | 32 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_px30.c | 54 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rv1126.c | 31 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3588.c | 23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| H A D | clk_rk3568.c | 39 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
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| /u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 1410 unsigned int fine_scalar_bits, unsigned int input_rate,
1419 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1427 if (input_rate == 0 || target_rate == 0)
1430 if (target_rate >= input_rate)
1435 max(min(input_rate / i / target_rate, cap), 1U);
1436 const unsigned int effective_rate = input_rate / i /
1409 clock_calc_best_scalar(unsigned int main_scaler_bits, unsigned int fine_scalar_bits, unsigned int input_rate, unsigned int target_rate, unsigned int *best_fine_scalar) argument
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