/u-boot/arch/arm/include/asm/arch-imx8ulp/ |
H A D | ddr.h | 12 struct dram_cfg_param { struct 19 struct dram_cfg_param *ctl_cfg; 22 struct dram_cfg_param *pi_cfg; 25 struct dram_cfg_param *phy_f1_cfg; 28 struct dram_cfg_param *phy_f2_cfg;
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/u-boot/arch/arm/include/asm/arch-imx9/ |
H A D | ddr.h | 60 struct dram_cfg_param { struct 66 struct dram_cfg_param ddrc_cfg[20]; 67 struct dram_cfg_param mr_cfg[10]; 74 struct dram_cfg_param *fsp_cfg; 80 struct dram_cfg_param *ddrc_cfg; 86 struct dram_cfg_param *ddrphy_cfg; 92 struct dram_cfg_param *ddrphy_trained_csr; 95 struct dram_cfg_param *ddrphy_pie; 107 void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); 144 extern struct dram_cfg_param ddrphy_trained_cs [all...] |
/u-boot/drivers/ddr/imx/phy/ |
H A D | ddrphy_train.c | 14 struct dram_cfg_param *dram_cfg;
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H A D | helper.c | 160 void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr, 181 struct dram_cfg_param *cfg; 192 cfg = (struct dram_cfg_param *)(saved_timing_base +
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/u-boot/board/variscite/imx8mn_var_som/ |
H A D | ddr4_timing.c | 13 static struct dram_cfg_param ddr_ddrc_cfg[] = { 113 static struct dram_cfg_param ddr_ddrphy_cfg[] = { 217 static struct dram_cfg_param ddr_fsp0_cfg[] = { 243 static struct dram_cfg_param ddr_fsp1_cfg[] = { 268 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { 295 static struct dram_cfg_param ddr_phy_pie[] = {
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/u-boot/drivers/ddr/imx/imx8ulp/ |
H A D | ddr_init.c | 220 struct dram_cfg_param *cfg; 230 cfg = (struct dram_cfg_param *)(saved_timing_base +
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/u-boot/board/gateworks/venice/ |
H A D | lpddr4_timing_imx8mn.c | 10 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 413 static struct dram_cfg_param ddr_phy_pie[] = { 983 static struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { 1093 static struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { 1246 static struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { 1283 static struct dram_cfg_param ddr_fsp1_cfg_1gb_single_die[] = { 1321 static struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = { 1359 static struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { 1446 static struct dram_cfg_param ddr_ddrc_cfg_2gb_single_die[] = { 1557 static struct dram_cfg_param ddr_ddrphy_cfg_2gb_single_di [all...] |
H A D | lpddr4_timing_imx8mm.c | 14 static struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { 737 struct dram_cfg_param lpddr4_phy_pie[] = { 1332 static struct dram_cfg_param ddr_ddrc_cfg_512mb[] = { 1443 static struct dram_cfg_param ddr_ddrphy_cfg_512mb[] = { 1647 static struct dram_cfg_param ddr_fsp0_cfg_512mb[] = { 1685 static struct dram_cfg_param ddr_fsp1_cfg_512mb[] = { 1724 static struct dram_cfg_param ddr_fsp2_cfg_512mb[] = { 1763 static struct dram_cfg_param ddr_fsp0_2d_cfg_512mb[] = { 1848 static struct dram_cfg_param lpddr4_ddrc_cfg_1gb[] = { 1958 static struct dram_cfg_param lpddr4_ddrphy_cfg_1g [all...] |
H A D | lpddr4_timing_imx8mp.c | 10 static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 733 static struct dram_cfg_param ddr_phy_pie[] = { 1321 struct dram_cfg_param ddr_ddrc_cfg_1gb_single_die[] = { 1436 struct dram_cfg_param ddr_ddrphy_cfg_1gb_single_die[] = { 1645 struct dram_cfg_param ddr_fsp0_cfg_1gb_single_die[] = { 1684 struct dram_cfg_param ddr_fsp1_cfg_1gb_single_die[] = { 1724 struct dram_cfg_param ddr_fsp2_cfg_1gb_single_die[] = { 1764 struct dram_cfg_param ddr_fsp0_2d_cfg_1gb_single_die[] = { 1854 static struct dram_cfg_param ddr_ddrc_cfg_4gb_dual_die[] = { 1969 static struct dram_cfg_param ddr_ddrphy_cfg_4gb_dual_di [all...] |
/u-boot/drivers/ddr/imx/imx9/ |
H A D | ddr_init.c | 77 struct dram_cfg_param *ddrc_config; 148 static u32 ddrc_get_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, unsigned int cfg_num, u32 reg) 160 static void ddrc_update_fsp_reg_setting(struct dram_cfg_param *ddrc_cfg, int cfg_num, 313 void update_mr_fsp_op0(struct dram_cfg_param *cfg, unsigned int num) 325 void save_trained_mr12_14(struct dram_cfg_param *cfg, u32 cfg_num, u32 mr12, u32 mr14)
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/u-boot/board/freescale/imx8mn_evk/ |
H A D | ddr4_timing_ld.c | 14 struct dram_cfg_param ddr_ddrc_cfg[] = { 114 struct dram_cfg_param ddr_ddrphy_cfg[] = { 218 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 745 struct dram_cfg_param ddr_fsp0_cfg[] = { 770 struct dram_cfg_param ddr_fsp1_cfg[] = { 796 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { 821 struct dram_cfg_param ddr_phy_pie[] = {
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H A D | ddr4_timing.c | 13 struct dram_cfg_param ddr_ddrc_cfg[] = { 110 struct dram_cfg_param ddr_ddrphy_cfg[] = { 214 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 741 struct dram_cfg_param ddr_fsp0_cfg[] = { 767 struct dram_cfg_param ddr_fsp1_cfg[] = { 792 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { 819 struct dram_cfg_param ddr_phy_pie[] = {
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H A D | lpddr4_timing.c | 12 struct dram_cfg_param ddr_ddrc_cfg[] = { 124 struct dram_cfg_param ddr_ddrphy_cfg[] = { 279 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 682 struct dram_cfg_param ddr_fsp0_cfg[] = { 757 struct dram_cfg_param ddr_fsp1_cfg[] = { 832 struct dram_cfg_param ddr_fsp2_cfg[] = { 907 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { 982 struct dram_cfg_param ddr_phy_pie[] = {
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H A D | lpddr4_timing_ld.c | 13 struct dram_cfg_param ddr_ddrc_cfg[] = { 123 struct dram_cfg_param ddr_ddrphy_cfg[] = { 277 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 680 struct dram_cfg_param ddr_fsp0_cfg[] = { 717 struct dram_cfg_param ddr_fsp1_cfg[] = { 755 struct dram_cfg_param ddr_fsp2_cfg[] = { 793 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { 831 struct dram_cfg_param ddr_phy_pie[] = {
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/u-boot/arch/arm/include/asm/arch-imx8m/ |
H A D | ddr.h | 673 struct dram_cfg_param { struct 681 struct dram_cfg_param *fsp_cfg; 687 struct dram_cfg_param *ddrc_cfg; 690 struct dram_cfg_param *ddrphy_cfg; 696 struct dram_cfg_param *ddrphy_trained_csr; 699 struct dram_cfg_param *ddrphy_pie; 711 void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); 750 extern struct dram_cfg_param ddrphy_trained_csr[];
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/u-boot/board/mntre/imx8mq_reform2/ |
H A D | lpddr4_timing.c | 12 static struct dram_cfg_param lpddr4_ddrc_cfg[] = { 113 static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { 278 static struct dram_cfg_param lpddr4_fsp0_cfg[] = { 317 static struct dram_cfg_param lpddr4_fsp1_cfg[] = { 357 static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { 398 static struct dram_cfg_param lpddr4_phy_pie[] = {
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/u-boot/board/bsh/imx8mn_smm_s2/ |
H A D | ddr3l_timing_256m.c | 16 struct dram_cfg_param ddr_ddrc_cfg[] = { 90 struct dram_cfg_param ddr_ddrphy_cfg[] = { 184 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 675 struct dram_cfg_param ddr_fsp0_cfg[] = { 695 struct dram_cfg_param ddr_fsp1_cfg[] = { 716 struct dram_cfg_param ddr_phy_pie[] = {
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H A D | ddr3l_timing_512m.c | 16 struct dram_cfg_param ddr_ddrc_cfg[] = { 90 struct dram_cfg_param ddr_ddrphy_cfg[] = { 184 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 675 struct dram_cfg_param ddr_fsp0_cfg[] = { 694 struct dram_cfg_param ddr_fsp1_cfg[] = { 715 struct dram_cfg_param ddr_phy_pie[] = {
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/u-boot/board/toradex/verdin-imx8mp/ |
H A D | lpddr4_timing.c | 18 struct dram_cfg_param ddr_ddrc_cfg_single_rank_patch[] = { 24 struct dram_cfg_param ddr_fsp0_cfg_single_rank_patch[] = { 29 struct dram_cfg_param ddr_fsp1_cfg_single_rank_patch[] = { 34 struct dram_cfg_param ddr_fsp2_cfg_single_rank_patch[] = { 39 struct dram_cfg_param ddr_fsp0_2d_cfg_single_rank_patch[] = { 44 struct dram_cfg_param ddr_ddrc_cfg[] = { 159 struct dram_cfg_param ddr_ddrphy_cfg[] = { 368 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 1091 struct dram_cfg_param ddr_fsp0_cfg[] = { 1130 struct dram_cfg_param ddr_fsp1_cf [all...] |
/u-boot/board/purism/librem5/ |
H A D | lpddr4_timing.c | 13 struct dram_cfg_param lpddr4_ddrc_cfg[] = { 138 struct dram_cfg_param lpddr4_ddrphy_cfg[] = { 332 struct dram_cfg_param lpddr4_fsp0_cfg[] = { 438 struct dram_cfg_param lpddr4_fsp1_cfg[] = { 520 struct dram_cfg_param lpddr4_fsp2_cfg[] = { 597 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { 691 struct dram_cfg_param lpddr4_phy_pie[] = {
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H A D | lpddr4_timing_b0.c | 13 static struct dram_cfg_param lpddr4_ddrc_cfg[] = { 136 static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { 321 static struct dram_cfg_param lpddr4_fsp0_cfg[] = { 399 static struct dram_cfg_param lpddr4_fsp1_cfg[] = { 475 static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { 554 static struct dram_cfg_param lpddr4_phy_pie[] = {
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/u-boot/board/freescale/imx8mq_evk/ |
H A D | lpddr4_timing.c | 13 struct dram_cfg_param lpddr4_ddrc_cfg[] = { 138 struct dram_cfg_param lpddr4_ddrphy_cfg[] = { 332 struct dram_cfg_param lpddr4_fsp0_cfg[] = { 438 struct dram_cfg_param lpddr4_fsp1_cfg[] = { 520 struct dram_cfg_param lpddr4_fsp2_cfg[] = { 597 struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { 691 struct dram_cfg_param lpddr4_phy_pie[] = {
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H A D | lpddr4_timing_b0.c | 13 static struct dram_cfg_param lpddr4_ddrc_cfg[] = { 136 static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { 321 static struct dram_cfg_param lpddr4_fsp0_cfg[] = { 399 static struct dram_cfg_param lpddr4_fsp1_cfg[] = { 475 static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { 554 static struct dram_cfg_param lpddr4_phy_pie[] = {
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/u-boot/board/beacon/imx8mn/ |
H A D | lpddr4_2g_timing.c | 12 struct dram_cfg_param ddr_ddrc_cfg[] = { 122 struct dram_cfg_param ddr_ddrphy_cfg[] = { 276 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 679 struct dram_cfg_param ddr_fsp0_cfg[] = { 716 struct dram_cfg_param ddr_fsp1_cfg[] = { 754 struct dram_cfg_param ddr_fsp2_cfg[] = { 792 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { 831 struct dram_cfg_param ddr_phy_pie[] = {
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/u-boot/board/freescale/imx8mm_evk/ |
H A D | lpddr4_timing.c | 11 struct dram_cfg_param ddr_ddrc_cfg[] = { 127 struct dram_cfg_param ddr_ddrphy_cfg[] = { 331 struct dram_cfg_param ddr_ddrphy_trained_csr[] = { 1053 struct dram_cfg_param ddr_fsp0_cfg[] = { 1091 struct dram_cfg_param ddr_fsp1_cfg[] = { 1130 struct dram_cfg_param ddr_fsp2_cfg[] = { 1169 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { 1209 struct dram_cfg_param ddr_phy_pie[] = {
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