#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
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#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
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#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
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#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
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#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7be5c4cb |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ddr: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
a29383da |
|
31-Jan-2023 |
Jacky Bai <ping.bai@nxp.com> |
ddr: imx: Update the ddr init flow on imx8ulp Update the ddr init flow to support LPDDR3 and PLL bypass mode. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
01aa4cd8 |
|
28-Oct-2021 |
Ye Li <ye.li@nxp.com> |
imx8ulp: ddr: Fix DDR frequency request issue After acking the requested frequency, should wait the ack bit clear by DDR controller and check the DFS interrupt for next request polling. Otherwise, the next polling of request bit will get previous value that DDR controller have not cleared it, so a wrong request frequency is used. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
b80ec768 |
|
28-Oct-2021 |
Jacky Bai <ping.bai@nxp.com> |
imx8ulp:ddr: saving the dram config timing data into sram On i.MX8ULP, The dram config timing need to be saved into sram for ddr retention when APD enter PD mode, so add this support on i.MX8ULP. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
|
#
7a6577fe |
|
07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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#
7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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#
7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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#
7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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#
7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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#
7a6577fe |
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07-Aug-2021 |
Ye Li <ye.li@nxp.com> |
ddr: Add DDR driver for iMX8ULP Add iMX8ULP DDR initialization driver which loads the DDR timing parameters and executes the training procedure. When enabling IMX8ULP_DRAM_PHY_PLL_BYPASS, using PHY PLL bypass mode to do DDR init Signed-off-by: Ye Li <ye.li@nxp.com>
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