/u-boot/arch/x86/cpu/intel_common/ |
H A D | pch.c | 14 dm_pci_write_config32(dev, SATA_SIRI, idx); 22 dm_pci_write_config32(dev, SATA_SIRI, idx); 23 dm_pci_write_config32(dev, SATA_SIRD, value);
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H A D | lpc.c | 34 dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1); 74 dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg);
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H A D | intel_opregion.c | 64 dm_pci_write_config32(dev, ASLS, opregion);
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/u-boot/arch/x86/cpu/broadwell/ |
H A D | me.c | 30 dm_pci_write_config32(dev, PCI_ME_H_GS, 54 dm_pci_write_config32(dev, PCI_ME_H_GS,
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H A D | northbridge.c | 116 dm_pci_write_config32(dev, PCIEXBAR + 4, 0); 118 dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1); 120 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); 121 dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1); 122 dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1); 136 dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
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H A D | adsp.c | 58 dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE); 86 dm_pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); 114 dm_pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ);
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H A D | sata.c | 69 dm_pci_write_config32(dev, 0x98, reg32); 80 dm_pci_write_config32(dev, 0x94, reg32); 201 dm_pci_write_config32(dev, 0x300, reg32); 205 dm_pci_write_config32(dev, 0x98, reg32); 210 dm_pci_write_config32(dev, 0x9c, reg32);
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H A D | pch.c | 46 dm_pci_write_config32(dev, PCH_RCBA, RCB_BASE_ADDRESS | 1); 48 dm_pci_write_config32(dev, PMBASE, ACPI_BASE_ADDRESS | 1); 50 dm_pci_write_config32(dev, GPIO_BASE, GPIO_BASE_ADDRESS | 1);
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/u-boot/board/intel/cougarcanyon2/ |
H A D | cougarcanyon2.c | 31 dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B | 33 dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
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/u-boot/arch/x86/cpu/ivybridge/ |
H A D | northbridge.c | 162 dm_pci_write_config32(dev, EPBAR, DEFAULT_EPBAR | 1); 163 dm_pci_write_config32(dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); 164 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); 165 dm_pci_write_config32(dev, MCHBAR + 4, (0LL + MCH_BASE_ADDRESS) >> 32); 167 dm_pci_write_config32(dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); 168 dm_pci_write_config32(dev, PCIEXBAR + 4, 170 dm_pci_write_config32(dev, DMIBAR, DEFAULT_DMIBAR | 1); 171 dm_pci_write_config32(dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); 236 dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
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H A D | lpc.c | 124 dm_pci_write_config32(pch, 0xb8, reg); 487 dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, 489 dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); 498 dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1); 499 dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
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H A D | early_me.c | 93 dm_pci_write_config32(dev, ETR3, etr3);
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H A D | sata.c | 27 dm_pci_write_config32(dev, IDE_CONFIG, reg32); 37 dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
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/u-boot/drivers/pci/ |
H A D | pci_auto.c | 70 dm_pci_write_config32(dev, bar, 0xffffffff); 94 dm_pci_write_config32(dev, bar + 4, 0xffffffff); 128 dm_pci_write_config32(dev, bar, (u32)bar_value); 133 dm_pci_write_config32(dev, bar, 141 dm_pci_write_config32(dev, bar, 0x00000000); 159 dm_pci_write_config32(dev, rom_addr, 0xfffffffe); 167 dm_pci_write_config32(dev, rom_addr, bar_value); 402 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 405 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0); 491 dm_pci_write_config32(de [all...] |
H A D | pci_rom.c | 99 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, 114 dm_pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address);
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/u-boot/arch/x86/cpu/queensbay/ |
H A D | tnc.c | 52 dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE); 53 dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
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/u-boot/drivers/bios_emulator/ |
H A D | atibios.c | 298 dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF); 326 dm_pci_write_config32(pcidev, reg, *base); 375 dm_pci_write_config32(pcidev, BIOSImageBAR, 0); 376 dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1); 398 dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress); 399 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10); 400 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14); 401 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18); 402 dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
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H A D | bios.c | 271 dm_pci_write_config32(_BE_env.vgaInfo.pcidev, 285 dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
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/u-boot/board/imgtec/malta/ |
H A D | malta.c | 238 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI, 240 dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
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/u-boot/arch/x86/cpu/apollolake/ |
H A D | fsp_m.c | 63 dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0,
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/u-boot/drivers/i2c/ |
H A D | designware_i2c_pci.c | 50 dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); 53 dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
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/u-boot/drivers/usb/host/ |
H A D | xhci-pci.c | 49 dm_pci_write_config32(dev, PCI_COMMAND, cmd);
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H A D | ehci-pci.c | 54 dm_pci_write_config32(dev, PCI_COMMAND, cmd);
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/u-boot/cmd/ |
H A D | pci.c | 94 dm_pci_write_config32(dev, reg_addr, 0xffffffff); 96 dm_pci_write_config32(dev, reg_addr, base_low); 110 dm_pci_write_config32(dev, reg_addr, 0xffffffff); 112 dm_pci_write_config32(dev, reg_addr, base_high);
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/u-boot/arch/x86/include/asm/ |
H A D | me_common.h | 370 dm_pci_write_config32(me_dev, offset, dword);
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