1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6#include <common.h> 7#include <dm.h> 8#include <init.h> 9#include <dm/device-internal.h> 10#include <pci.h> 11#include <asm/io.h> 12#include <asm/irq.h> 13#include <asm/post.h> 14#include <asm/arch/device.h> 15#include <asm/arch/tnc.h> 16#include <asm/fsp1/fsp_support.h> 17#include <asm/processor.h> 18 19static int __maybe_unused disable_igd(void) 20{ 21 struct udevice *igd = NULL; 22 struct udevice *sdvo = NULL; 23 int ret; 24 25 /* 26 * In case the IGD and SDVO devices were already in disabled state, 27 * we should return and not proceed any further. 28 */ 29 dm_pci_bus_find_bdf(TNC_IGD, &igd); 30 dm_pci_bus_find_bdf(TNC_SDVO, &sdvo); 31 if (!igd || !sdvo) 32 return 0; 33 34 /* 35 * According to Atom E6xx datasheet, setting VGA Disable (bit17) 36 * of Graphics Controller register (offset 0x50) prevents IGD 37 * (D2:F0) from reporting itself as a VGA display controller 38 * class in the PCI configuration space, and should also prevent 39 * it from responding to VGA legacy memory range and I/O addresses. 40 * 41 * However test result shows that with just VGA Disable bit set and 42 * a PCIe graphics card connected to one of the PCIe controllers on 43 * the E6xx, accessing the VGA legacy space still causes system hang. 44 * After a number of attempts, it turns out besides VGA Disable bit, 45 * the SDVO (D3:F0) device should be disabled to make it work. 46 * 47 * To simplify, use the Function Disable register (offset 0xc4) 48 * to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these 49 * two devices will be completely disabled (invisible in the PCI 50 * configuration space) unless a system reset is performed. 51 */ 52 dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE); 53 dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE); 54 55 /* 56 * After setting the function disable bit, IGD and SDVO devices will 57 * disappear in the PCI configuration space. This however creates an 58 * inconsistent state from a driver model PCI controller point of view, 59 * as these two PCI devices are still attached to its parent's child 60 * device list as maintained by the driver model. Some driver model PCI 61 * APIs like dm_pci_find_class(), are referring to the list to speed up 62 * the finding process instead of re-enumerating the whole PCI bus, so 63 * it gets the stale cached data which is wrong. 64 * 65 * Note x86 PCI enueration normally happens twice, in pre-relocation 66 * phase and post-relocation. One option might be to call disable_igd() 67 * in one of the pre-relocation initialization hooks so that it gets 68 * disabled in the first round, and when it comes to the second round 69 * driver model PCI will construct a correct list. Unfortunately this 70 * does not work as Intel FSP is used on this platform to perform low 71 * level initialization, and fsp_init_phase_pci() is called only once 72 * in the post-relocation phase. If we disable IGD and SDVO devices, 73 * fsp_init_phase_pci() simply hangs and never returns. 74 * 75 * So the only option we have is to manually remove these two devices. 76 */ 77 ret = device_remove(igd, DM_REMOVE_NORMAL); 78 if (ret) 79 return ret; 80 ret = device_unbind(igd); 81 if (ret) 82 return ret; 83 ret = device_remove(sdvo, DM_REMOVE_NORMAL); 84 if (ret) 85 return ret; 86 ret = device_unbind(sdvo); 87 if (ret) 88 return ret; 89 90 return 0; 91} 92 93int arch_cpu_init(void) 94{ 95 post_code(POST_CPU_INIT); 96 97 return x86_cpu_init_f(); 98} 99 100static void tnc_irq_init(void) 101{ 102 struct tnc_rcba *rcba; 103 u32 base; 104 105 pci_read_config32(TNC_LPC, LPC_RCBA, &base); 106 base &= ~MEM_BAR_EN; 107 rcba = (struct tnc_rcba *)base; 108 109 /* Make sure all internal PCI devices are using INTA */ 110 writel(INTA, &rcba->d02ip); 111 writel(INTA, &rcba->d03ip); 112 writel(INTA, &rcba->d27ip); 113 writel(INTA, &rcba->d31ip); 114 writel(INTA, &rcba->d23ip); 115 writel(INTA, &rcba->d24ip); 116 writel(INTA, &rcba->d25ip); 117 writel(INTA, &rcba->d26ip); 118 119 /* 120 * Route TunnelCreek PCI device interrupt pin to PIRQ 121 * 122 * Since PCIe downstream ports received INTx are routed to PIRQ 123 * A/B/C/D directly and not configurable, we have to route PCIe 124 * root ports' INTx to PIRQ A/B/C/D as well. For other devices 125 * on TunneCreek, route them to PIRQ E/F/G/H. 126 */ 127 writew(PIRQE, &rcba->d02ir); 128 writew(PIRQF, &rcba->d03ir); 129 writew(PIRQG, &rcba->d27ir); 130 writew(PIRQH, &rcba->d31ir); 131 writew(PIRQA, &rcba->d23ir); 132 writew(PIRQB, &rcba->d24ir); 133 writew(PIRQC, &rcba->d25ir); 134 writew(PIRQD, &rcba->d26ir); 135} 136 137int arch_early_init_r(void) 138{ 139 int ret = 0; 140 141#ifdef CONFIG_DISABLE_IGD 142 ret = disable_igd(); 143#endif 144 145 tnc_irq_init(); 146 147 return ret; 148} 149