1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2011 The Chromium Authors 4 */ 5 6#include <common.h> 7#include <dm.h> 8#include <asm/global_data.h> 9#include <asm/io.h> 10#include <asm/mrc_common.h> 11#include <asm/arch/iomap.h> 12#include <asm/arch/pch.h> 13#include <asm/arch/pei_data.h> 14 15__weak asmlinkage void sdram_console_tx_byte(unsigned char byte) 16{ 17#ifdef DEBUG 18 putc(byte); 19#endif 20} 21 22void broadwell_fill_pei_data(struct pei_data *pei_data) 23{ 24 pei_data->pei_version = PEI_VERSION; 25 pei_data->board_type = BOARD_TYPE_ULT; 26 pei_data->pciexbar = MCFG_BASE_ADDRESS; 27 pei_data->smbusbar = SMBUS_BASE_ADDRESS; 28 pei_data->ehcibar = EARLY_EHCI_BAR; 29 pei_data->xhcibar = EARLY_XHCI_BAR; 30 pei_data->gttbar = EARLY_GTT_BAR; 31 pei_data->pmbase = ACPI_BASE_ADDRESS; 32 pei_data->gpiobase = GPIO_BASE_ADDRESS; 33 pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; 34 pei_data->temp_mmio_base = EARLY_TEMP_MMIO; 35 pei_data->tx_byte = sdram_console_tx_byte; 36 pei_data->ddr_refresh_2x = 1; 37} 38 39static void pei_data_usb2_port(struct pei_data *pei_data, int port, uint length, 40 uint enable, uint oc_pin, uint location) 41{ 42 pei_data->usb2_ports[port].length = length; 43 pei_data->usb2_ports[port].enable = enable; 44 pei_data->usb2_ports[port].oc_pin = oc_pin; 45 pei_data->usb2_ports[port].location = location; 46} 47 48static void pei_data_usb3_port(struct pei_data *pei_data, int port, uint enable, 49 uint oc_pin, uint fixed_eq) 50{ 51 pei_data->usb3_ports[port].enable = enable; 52 pei_data->usb3_ports[port].oc_pin = oc_pin; 53 pei_data->usb3_ports[port].fixed_eq = fixed_eq; 54} 55 56void mainboard_fill_pei_data(struct pei_data *pei_data) 57{ 58 /* DQ byte map for Samus board */ 59 const u8 dq_map[2][6][2] = { 60 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, 61 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, 62 { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, 63 { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; 64 /* DQS CPU<>DRAM map for Samus board */ 65 const u8 dqs_map[2][8] = { 66 { 2, 0, 1, 3, 6, 4, 7, 5 }, 67 { 2, 1, 0, 3, 6, 5, 4, 7 } }; 68 69 pei_data->ec_present = 1; 70 71 /* One installed DIMM per channel */ 72 pei_data->dimm_channel0_disabled = 2; 73 pei_data->dimm_channel1_disabled = 2; 74 75 memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); 76 memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); 77 78 /* P0: HOST PORT */ 79 pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, 80 USB_PORT_BACK_PANEL); 81 /* P1: HOST PORT */ 82 pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, 83 USB_PORT_BACK_PANEL); 84 /* P2: RAIDEN */ 85 pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, 86 USB_PORT_BACK_PANEL); 87 /* P3: SD CARD */ 88 pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, 89 USB_PORT_INTERNAL); 90 /* P4: RAIDEN */ 91 pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, 92 USB_PORT_BACK_PANEL); 93 /* P5: WWAN (Disabled) */ 94 pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, 95 USB_PORT_SKIP); 96 /* P6: CAMERA */ 97 pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, 98 USB_PORT_INTERNAL); 99 /* P7: BT */ 100 pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, 101 USB_PORT_INTERNAL); 102 103 /* P1: HOST PORT */ 104 pei_data_usb3_port(pei_data, 0, 1, 0, 0); 105 /* P2: HOST PORT */ 106 pei_data_usb3_port(pei_data, 1, 1, 1, 0); 107 /* P3: RAIDEN */ 108 pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); 109 /* P4: RAIDEN */ 110 pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); 111} 112 113static int broadwell_northbridge_early_init(struct udevice *dev) 114{ 115 /* Move earlier? */ 116 dm_pci_write_config32(dev, PCIEXBAR + 4, 0); 117 /* 64MiB - 0-63 buses */ 118 dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1); 119 120 dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1); 121 dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1); 122 dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1); 123 writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR); 124 writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR); 125 126 /* Set C0000-FFFFF to access RAM on both reads and writes */ 127 dm_pci_write_config8(dev, PAM0, 0x30); 128 dm_pci_write_config8(dev, PAM1, 0x33); 129 dm_pci_write_config8(dev, PAM2, 0x33); 130 dm_pci_write_config8(dev, PAM3, 0x33); 131 dm_pci_write_config8(dev, PAM4, 0x33); 132 dm_pci_write_config8(dev, PAM5, 0x33); 133 dm_pci_write_config8(dev, PAM6, 0x33); 134 135 /* Device enable: IGD and Mini-HD */ 136 dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); 137 138 return 0; 139} 140 141static int broadwell_northbridge_probe(struct udevice *dev) 142{ 143 if (!(gd->flags & GD_FLG_RELOC)) 144 return broadwell_northbridge_early_init(dev); 145 146 return 0; 147} 148 149static const struct udevice_id broadwell_northbridge_ids[] = { 150 { .compatible = "intel,broadwell-northbridge" }, 151 { } 152}; 153 154U_BOOT_DRIVER(broadwell_northbridge_drv) = { 155 .name = "broadwell_northbridge", 156 .id = UCLASS_NORTHBRIDGE, 157 .of_match = broadwell_northbridge_ids, 158 .probe = broadwell_northbridge_probe, 159}; 160