1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 6#include <common.h> 7#include <dm.h> 8#include <errno.h> 9#include <fdtdec.h> 10#include <pch.h> 11#include <pci.h> 12#include <asm/global_data.h> 13#include <asm/intel_regs.h> 14#include <asm/io.h> 15#include <asm/lpc_common.h> 16#include <linux/bitops.h> 17 18DECLARE_GLOBAL_DATA_PTR; 19 20/* Enable Prefetching and Caching */ 21static void enable_spi_prefetch(struct udevice *pch) 22{ 23 u8 reg8; 24 25 dm_pci_read_config8(pch, 0xdc, ®8); 26 reg8 &= ~(3 << 2); 27 reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ 28 dm_pci_write_config8(pch, 0xdc, reg8); 29} 30 31static void enable_port80_on_lpc(struct udevice *pch) 32{ 33 /* Enable port 80 POST on LPC */ 34 dm_pci_write_config32(pch, PCH_RCBA_BASE, RCB_BASE_ADDRESS | 1); 35 clrbits_le32(RCB_REG(GCS), 4); 36} 37 38/** 39 * lpc_early_init() - set up LPC serial ports and other early things 40 * 41 * @dev: LPC device 42 * Return: 0 if OK, -ve on error 43 */ 44int lpc_common_early_init(struct udevice *dev) 45{ 46 struct udevice *pch = dev->parent; 47 struct reg_info { 48 u32 base; 49 u32 size; 50 } values[4], *ptr; 51 int count; 52 int i; 53 54 count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev), 55 "intel,gen-dec", (u32 *)values, 56 sizeof(values) / (sizeof(u32))); 57 if (count < 0) 58 return -EINVAL; 59 60 /* Set COM1/COM2 decode range */ 61 dm_pci_write_config16(pch, LPC_IO_DEC, 0x0010); 62 63 /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ 64 dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | MC_LPC_EN | 65 GAMEL_LPC_EN | COMA_LPC_EN); 66 67 /* Write all registers but use 0 if we run out of data */ 68 count = count * sizeof(u32) / sizeof(values[0]); 69 for (i = 0, ptr = values; i < ARRAY_SIZE(values); i++, ptr++) { 70 u32 reg = 0; 71 72 if (i < count) 73 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); 74 dm_pci_write_config32(pch, LPC_GENX_DEC(i), reg); 75 } 76 77 enable_spi_prefetch(pch); 78 79 /* This is already done in start.S, but let's do it in C */ 80 enable_port80_on_lpc(pch); 81 82 return 0; 83} 84 85int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect) 86{ 87 uint8_t bios_cntl; 88 89 /* Adjust the BIOS write protect and SMM BIOS Write Protect Disable */ 90 dm_pci_read_config8(dev, bios_ctrl, &bios_cntl); 91 if (protect) { 92 bios_cntl &= ~BIOS_CTRL_BIOSWE; 93 bios_cntl |= BIT(5); 94 } else { 95 bios_cntl |= BIOS_CTRL_BIOSWE; 96 bios_cntl &= ~BIT(5); 97 } 98 dm_pci_write_config8(dev, bios_ctrl, bios_cntl); 99 100 return 0; 101} 102