/u-boot/drivers/video/rockchip/ |
H A D | rk_mipi.c | 205 u64 ddr_clk = priv->phy_clk; local 232 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3; 243 if (ddr_clk / (MHz) <= freq_rang[i][0]) 257 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz 273 if ((ddr_clk * i % refclk < remain) && 274 (ddr_clk * i / refclk) < max_fbdiv) { 276 remain = ddr_clk * i % refclk; 279 fbdiv = ddr_clk * prediv / refclk; 280 ddr_clk = refclk * fbdiv / prediv; 281 priv->phy_clk = ddr_clk; [all...] |
/u-boot/drivers/clk/mtmips/ |
H A D | clk-mt7621.c | 50 int ddr_clk; member in struct:mt7621_clk_priv 125 return priv->ddr_clk; 194 u32 xtal_clk, xtal_div, ffiv, ffrac, cpu_clk, ddr_clk; local 233 ddr_clk = fb * xtal_clk / xtal_div; 237 ddr_clk *= 2; 241 priv->ddr_clk = ddr_clk;
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/u-boot/drivers/ram/sifive/ |
H A D | sifive_ddr.c | 91 struct clk ddr_clk; member in struct:sifive_ddr_info 348 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 359 ret = clk_set_rate(&priv->ddr_clk, clock); 366 ret = clk_enable(&priv->ddr_clk);
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/u-boot/arch/mips/mach-mtmips/mt7621/ |
H A D | init.c | 32 u32 cpu_clk, ddr_clk, bus_clk, xtal_clk; local 71 ddr_clk = clk_get_rate(&clk); 81 cpu_clk / 1000000, ddr_clk / 500000, bus_clk / 1000000,
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/u-boot/drivers/ram/k3-ddrss/ |
H A D | k3-ddrss.c | 135 struct clk ddr_clk; member in struct:k3_ddrss_desc 224 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); 226 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2); 228 clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0); 272 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1); 275 ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0); 370 ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
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/u-boot/drivers/ram/stm32mp1/ |
H A D | stm32mp1_ram.c | 38 unsigned long ddr_clk; local 61 ddr_clk = abs(ddrphy_clk - mem_speed * 1000); 62 if (ddr_clk > (mem_speed * 100)) {
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/u-boot/arch/arm/mach-omap2/ |
H A D | clocks-common.c | 272 u32 ddr_clk, sys_clk_khz, omap_rev, divider; local 283 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / 300 ddr_clk = ddr_clk / divider / core_dpll_params->m2; 301 ddr_clk *= 1000; /* convert to Hz */ 302 debug("ddr_clk %d\n ", ddr_clk); 304 return ddr_clk;
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/u-boot/drivers/ram/aspeed/ |
H A D | sdram_ast2500.c | 70 struct clk ddr_clk; member in struct:dram_info 336 int ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 349 clk_set_rate(&priv->ddr_clk, priv->clock_rate);
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H A D | sdram_ast2600.c | 545 struct clk ddr_clk; member in struct:dram_info
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/u-boot/drivers/ram/rockchip/ |
H A D | dmc-rk3368.c | 30 struct clk ddr_clk; member in struct:dram_info 813 ret = clk_set_rate(&priv->ddr_clk, 2 * params->ddr_freq); 949 priv->ddr_clk.id = CLK_DDR; 950 ret = clk_request(dev_clk, &priv->ddr_clk);
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H A D | sdram_rk3188.c | 40 struct clk ddr_clk; member in struct:dram_info 726 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); 910 priv->ddr_clk.id = CLK_DDR; 911 ret = clk_request(dev_clk, &priv->ddr_clk);
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H A D | sdram_rk3066.c | 40 struct clk ddr_clk; member in struct:rk3066_dmc_dram_info 696 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); 843 priv->ddr_clk.id = CLK_DDR; 844 ret = clk_request(dev_clk, &priv->ddr_clk);
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H A D | sdram_rk322x.c | 36 struct clk ddr_clk; member in struct:dram_info 691 ret = clk_set_rate(&dram->ddr_clk, 803 priv->ddr_clk.id = CLK_DDR; 804 ret = clk_request(dev_clk, &priv->ddr_clk);
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H A D | sdram_rk3288.c | 42 struct clk ddr_clk; member in struct:dram_info 802 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); 1078 priv->ddr_clk.id = CLK_DDR; 1079 ret = clk_request(dev_clk, &priv->ddr_clk);
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H A D | sdram_rk3328.c | 28 struct clk ddr_clk; member in struct:dram_info
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H A D | sdram_rk3399.c | 70 struct clk ddr_clk; member in struct:dram_info 2504 ret_clk = clk_set_rate(&dram->ddr_clk, hz); 3118 ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->ddr_clk); 3120 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 3127 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
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/u-boot/drivers/ddr/altera/ |
H A D | sdram_n5x.c | 1195 struct clk *ddr_clk; local 1199 ddr_clk = devm_clk_get(dev, "mem_clk"); 1200 if (!IS_ERR(ddr_clk)) { 1201 ret = clk_enable(ddr_clk); 1207 ret = PTR_ERR(ddr_clk);
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