#
d678a59d |
|
18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
41b7743e |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ram: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> |
#
5fecea17 |
|
27-Sep-2023 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
treewide: use dev_read_addr_*_ptr() where appropriate A follow-up to commit 842fb5de424e ("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer") and commit 320a1938b6f7 ("drivers: use devfdt_get_addr_index_ptr when cast to pointer"). In addition to using the *_ptr variants of these functions where the address is cast to a pointer, this also changes devfdt_get_addr_*() to dev_read_addr_*() in a few places. Some variable and field types are changed from fdt_addr_t or phys_addr_t to void* where the cast was happening later. This patch fixes a number of compile warnings when building a 32bit U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error handling where the return value of dev_read_addr() etc. was checked for NULL instead of FDT_ADDR_T_NONE. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
af7c33c1 |
|
17-Jul-2023 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: do not touch ctrl regs during training During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com> |
#
f54febe1 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: add am62a controller support TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
270f7fd2 |
|
08-Apr-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Allow use of dt provided initial frequency Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
b4c80f24 |
|
06-Apr-2022 |
Dominic Rath <rath@ibv-augsburg.net> |
ram: k3-ddrss: Fix register name and explain its usage The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> |
#
f861ce90 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce ECC Functionality for full memory space Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
71eb5274 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a48fc5cc |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
1a99bec0 |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for multiple instances of DDR subsystems The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
41b7743e |
|
01-May-2024 |
Tom Rini <trini@konsulko.com> |
ram: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> |
#
5fecea17 |
|
27-Sep-2023 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
treewide: use dev_read_addr_*_ptr() where appropriate A follow-up to commit 842fb5de424e ("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer") and commit 320a1938b6f7 ("drivers: use devfdt_get_addr_index_ptr when cast to pointer"). In addition to using the *_ptr variants of these functions where the address is cast to a pointer, this also changes devfdt_get_addr_*() to dev_read_addr_*() in a few places. Some variable and field types are changed from fdt_addr_t or phys_addr_t to void* where the cast was happening later. This patch fixes a number of compile warnings when building a 32bit U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error handling where the return value of dev_read_addr() etc. was checked for NULL instead of FDT_ADDR_T_NONE. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
af7c33c1 |
|
17-Jul-2023 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: do not touch ctrl regs during training During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com> |
#
f54febe1 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: add am62a controller support TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
270f7fd2 |
|
08-Apr-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Allow use of dt provided initial frequency Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
b4c80f24 |
|
06-Apr-2022 |
Dominic Rath <rath@ibv-augsburg.net> |
ram: k3-ddrss: Fix register name and explain its usage The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> |
#
f861ce90 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce ECC Functionality for full memory space Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
71eb5274 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a48fc5cc |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
1a99bec0 |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for multiple instances of DDR subsystems The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com> |
#
5fecea17 |
|
27-Sep-2023 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
treewide: use dev_read_addr_*_ptr() where appropriate A follow-up to commit 842fb5de424e ("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer") and commit 320a1938b6f7 ("drivers: use devfdt_get_addr_index_ptr when cast to pointer"). In addition to using the *_ptr variants of these functions where the address is cast to a pointer, this also changes devfdt_get_addr_*() to dev_read_addr_*() in a few places. Some variable and field types are changed from fdt_addr_t or phys_addr_t to void* where the cast was happening later. This patch fixes a number of compile warnings when building a 32bit U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error handling where the return value of dev_read_addr() etc. was checked for NULL instead of FDT_ADDR_T_NONE. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
af7c33c1 |
|
17-Jul-2023 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: do not touch ctrl regs during training During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com> |
#
f54febe1 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: add am62a controller support TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
270f7fd2 |
|
08-Apr-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Allow use of dt provided initial frequency Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
b4c80f24 |
|
06-Apr-2022 |
Dominic Rath <rath@ibv-augsburg.net> |
ram: k3-ddrss: Fix register name and explain its usage The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> |
#
f861ce90 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce ECC Functionality for full memory space Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
71eb5274 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a48fc5cc |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
1a99bec0 |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for multiple instances of DDR subsystems The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
5fecea17 |
|
27-Sep-2023 |
Matthias Schiffer <matthias.schiffer@ew.tq-group.com> |
treewide: use dev_read_addr_*_ptr() where appropriate A follow-up to commit 842fb5de424e ("drivers: use devfdt_get_addr_size_index_ptr when cast to pointer") and commit 320a1938b6f7 ("drivers: use devfdt_get_addr_index_ptr when cast to pointer"). In addition to using the *_ptr variants of these functions where the address is cast to a pointer, this also changes devfdt_get_addr_*() to dev_read_addr_*() in a few places. Some variable and field types are changed from fdt_addr_t or phys_addr_t to void* where the cast was happening later. This patch fixes a number of compile warnings when building a 32bit U-Boot with CONFIG_PHYS_64BIT=y. In some places, it also fixes error handling where the return value of dev_read_addr() etc. was checked for NULL instead of FDT_ADDR_T_NONE. Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
af7c33c1 |
|
17-Jul-2023 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: do not touch ctrl regs during training During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com> |
#
f54febe1 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: add am62a controller support TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
270f7fd2 |
|
08-Apr-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Allow use of dt provided initial frequency Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
b4c80f24 |
|
06-Apr-2022 |
Dominic Rath <rath@ibv-augsburg.net> |
ram: k3-ddrss: Fix register name and explain its usage The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> |
#
f861ce90 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce ECC Functionality for full memory space Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
71eb5274 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a48fc5cc |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
1a99bec0 |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for multiple instances of DDR subsystems The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
af7c33c1 |
|
17-Jul-2023 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: do not touch ctrl regs during training During LPDDR initialization we will loop through a series of frequency changes in order to train at the various operating frequencies. During this training, accessing the DRAM_CLASS bitfield could happen during a frequency change and cause the read to hang. Store the DRAM type into the main structure to avoid multiple readings while the independent phy is training. Signed-off-by: Bryan Brattlof <bb@ti.com> |
#
f54febe1 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: add am62a controller support TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
270f7fd2 |
|
08-Apr-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Allow use of dt provided initial frequency Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
b4c80f24 |
|
06-Apr-2022 |
Dominic Rath <rath@ibv-augsburg.net> |
ram: k3-ddrss: Fix register name and explain its usage The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> |
#
f861ce90 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce ECC Functionality for full memory space Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
71eb5274 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a48fc5cc |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
1a99bec0 |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for multiple instances of DDR subsystems The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
f54febe1 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
ram: k3-ddrss: add am62a controller support TI's am62a family of SoCs uses a new 32bit DDR controller that shares much of the same functionality with the existing am64 and j721e controllers. Select this controller by default when u-boot is build for the am62a Signed-off-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> |
#
270f7fd2 |
|
08-Apr-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Allow use of dt provided initial frequency Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
b4c80f24 |
|
06-Apr-2022 |
Dominic Rath <rath@ibv-augsburg.net> |
ram: k3-ddrss: Fix register name and explain its usage The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> |
#
f861ce90 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce ECC Functionality for full memory space Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
71eb5274 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a48fc5cc |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
1a99bec0 |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for multiple instances of DDR subsystems The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
270f7fd2 |
|
08-Apr-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Allow use of dt provided initial frequency Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR frequency that is set for lpddr4 before initialization of the controller. Make this optional and continue to use PLL bypass frequency as is done currently if ti,ddr-freq0 is not provided. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
b4c80f24 |
|
06-Apr-2022 |
Dominic Rath <rath@ibv-augsburg.net> |
ram: k3-ddrss: Fix register name and explain its usage The k3-ddrss driver wants to configure the DDRSS_V2A_CTL_REG to reflect the maximum possible SDRAM of 2 GB for AM64x (instead of the register's default that says 8 GB, which the AM64x DDR controller wouldn't support). The offset 0x20 was correct, but the register name DDRSS_V2A_R1_MAT_REG was that of the next register at offset 0x24. Signed-off-by: Dominic Rath <rath@ibv-augsburg.net> |
#
f861ce90 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce ECC Functionality for full memory space Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
71eb5274 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a48fc5cc |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
1a99bec0 |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for multiple instances of DDR subsystems The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
f861ce90 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce ECC Functionality for full memory space Introduce ECC Functionality for full memory space as implemented in the DDRSS. The following is done to accomplish this: * Introduce a memory region "ss" to allow dt to provide DDRSS region, which is not the same as "ctl" which is the controller region. * Introduce a "ti,ecc-enable" flag which allows a memorycontroller instance to enable ecc. * Introduce functionality to properly program the DDRSS registers to enable ECC for the full DDR memory space if enabled with above flag. * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to account from DDR memory that must be reserved for ECC operation. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
71eb5274 |
|
16-Mar-2022 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs The current address being read from dt actually represents the ddrss_ctl memory region, while ddrss_ss region is something else. Introduce ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper purpose later so that we can avoid confusion. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a48fc5cc |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
1a99bec0 |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for multiple instances of DDR subsystems The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a48fc5cc |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems In Multi DDR subystems with interleaving support, the following needs to configured, - interleaving granular size and region - EMIFs to be enabled - EMIFs with ecc to be enabled - EMIF separated or interleaved - number of cycles of unsuccessful EMIF arbitration to wait before arbitrating for a different EMIF port, by default set to 3 Add support for configuring all the above by using a MSMC device Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
1a99bec0 |
|
25-Jan-2022 |
Aswath Govindraju <a-govindraju@ti.com> |
ram: k3-ddrss: Add support for multiple instances of DDR subsystems The current driver only supports single instance of DRR subsystem. Add support for probing multiple instances of DDR subsystem. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> |
#
0cf207ec |
|
27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
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2ce6dedf |
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11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
2ce6dedf |
|
11-May-2021 |
Lokesh Vutla <lokeshvutla@ti.com> |
ram: k3-ddrss: Enable vtt regulator if present Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
9f9b5c1c |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce support for AM642 SoCs Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |
#
a8c13c77 |
|
11-May-2021 |
Dave Gerlach <d-gerlach@ti.com> |
ram: k3-ddrss: Introduce common driver with J7 SoC support Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> |