Searched refs:ddr (Results 1 - 25 of 247) sorted by relevance

12345678910

/u-boot/post/cpu/mpc83xx/
H A Decc.c26 static inline void ecc_clear(ddr83xx_t *ddr) argument
29 __raw_writel(0, &ddr->capture_address);
30 __raw_writel(0, &ddr->capture_data_hi);
31 __raw_writel(0, &ddr->capture_data_lo);
32 __raw_writel(0, &ddr->capture_ecc);
33 __raw_writel(0, &ddr->capture_attributes);
36 out_be32(&ddr->err_sbe, 1 << ECC_ERROR_MAN_SBET_SHIFT);
39 out_be32(&ddr->err_detect, ECC_ERROR_DETECT_MME |\
53 ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; local
[all...]
/u-boot/drivers/ddr/fsl/
H A Darm_ddr_gen3.c36 struct ccsr_ddr __iomem *ddr; local
43 ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
47 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
52 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
57 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
69 ddr_out32(&ddr->eor, regs->ddr_eor);
72 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
73 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
74 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
77 ddr_out32(&ddr
[all...]
H A Dfsl_ddr_gen4.c58 struct ccsr_ddr __iomem *ddr; local
89 ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
93 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
98 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
103 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
116 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
119 ddr_out32(&ddr->eor, regs->ddr_eor);
121 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
126 ddr_out32(&ddr->cs0_bnds,
128 ddr_out32(&ddr
[all...]
H A Dmpc85xx_ddr_gen3.c30 struct ccsr_ddr __iomem *ddr; local
55 ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
59 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR;
64 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR;
69 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
81 out_be32(&ddr->eor, regs->ddr_eor);
104 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
105 out_be32(&ddr->cs0_config, regs->cs[i].config);
106 out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
109 out_be32(&ddr
[all...]
H A Dmpc85xx_ddr_gen1.c20 struct ccsr_ddr __iomem *ddr = local
30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
31 out_be32(&ddr->cs0_config, regs->cs[i].config);
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
35 out_be32(&ddr->cs1_config, regs->cs[i].config);
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
39 out_be32(&ddr->cs2_config, regs->cs[i].config);
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
43 out_be32(&ddr->cs3_config, regs->cs[i].config);
47 out_be32(&ddr
73 struct ccsr_ddr __iomem *ddr = local
[all...]
H A Dmpc85xx_ddr_gen2.c20 struct ccsr_ddr __iomem *ddr = local
50 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
51 out_be32(&ddr->cs0_config, regs->cs[i].config);
54 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
55 out_be32(&ddr->cs1_config, regs->cs[i].config);
58 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
59 out_be32(&ddr->cs2_config, regs->cs[i].config);
62 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
63 out_be32(&ddr->cs3_config, regs->cs[i].config);
67 out_be32(&ddr
[all...]
H A Dctrl_regs.c150 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, argument
227 ddr->cs[i].config = (0
246 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
251 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr) argument
255 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
256 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
297 fsl_ddr_cfg_regs_t *ddr,
440 ddr->timing_cfg_0 = (0
450 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
456 fsl_ddr_cfg_regs_t *ddr,
296 set_timing_cfg_0(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const dimm_params_t *dimm_params) argument
455 set_timing_cfg_3(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, unsigned int additive_latency) argument
507 set_timing_cfg_1(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency) argument
635 set_timing_cfg_2(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, unsigned int additive_latency) argument
728 set_ddr_sdram_rcw(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm) argument
784 set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm) argument
874 set_ddr_sdram_cfg_2(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const unsigned int unq_mrs_en) argument
976 set_ddr_sdram_mode_2(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) argument
1064 set_ddr_sdram_mode_2(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) argument
1140 set_ddr_sdram_mode_2(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) argument
1159 set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) argument
1271 set_ddr_sdram_mode_10(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) argument
1327 set_ddr_sdram_interval(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm) argument
1349 set_ddr_sdram_mode(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, unsigned int additive_latency, const unsigned int unq_mrs_en) argument
1520 set_ddr_sdram_mode(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, unsigned int additive_latency, const unsigned int unq_mrs_en) argument
1716 set_ddr_sdram_mode(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, unsigned int additive_latency, const unsigned int unq_mrs_en) argument
1850 set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) argument
1864 set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr) argument
1872 set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr) argument
1884 set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) argument
1926 set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency) argument
1954 set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) argument
1972 set_timing_cfg_7(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm) argument
2023 set_timing_cfg_8(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency) argument
2075 set_timing_cfg_9(const unsigned int ctrl_num, fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm) argument
2096 set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr, const dimm_params_t *dimm_params) argument
2141 set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) argument
2167 set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) argument
2204 set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, const memctl_options_t *popts) argument
2278 set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it) argument
2284 set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) argument
2292 set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) argument
2298 set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts) argument
2305 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) argument
2324 compute_fsl_memctl_config_regs(const unsigned int ctrl_num, const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_params, unsigned int dbw_cap_adj, unsigned int size_only) argument
2579 struct ccsr_ddr __iomem *ddr = local
[all...]
/u-boot/arch/mips/mach-ath79/qca956x/
H A DMakefile5 obj-y += ddr.o qca956x-ddr-tap.o
/u-boot/arch/powerpc/cpu/mpc83xx/
H A Decc.c18 struct ccsr_ddr __iomem *ddr = &immap->ddr; local
20 ddr83xx_t *ddr = &immap->ddr; local
24 (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
29 (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
31 (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
33 (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
38 (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
40 (ddr
102 struct ccsr_ddr __iomem *ddr = &immap->ddr; local
104 ddr83xx_t *ddr = &immap->ddr; local
[all...]
/u-boot/board/socrates/
H A Dsdram.c28 struct ccsr_ddr __iomem *ddr = local
34 ddr->cs0_config = 0;
35 ddr->sdram_cfg = 0;
37 ddr->cs0_bnds = CFG_SYS_DDR_CS0_BNDS;
38 ddr->cs0_config = CFG_SYS_DDR_CS0_CONFIG;
39 ddr->timing_cfg_0 = CFG_SYS_DDR_TIMING_0;
40 ddr->timing_cfg_1 = CFG_SYS_DDR_TIMING_1;
41 ddr->timing_cfg_2 = CFG_SYS_DDR_TIMING_2;
42 ddr->sdram_mode = CFG_SYS_DDR_MODE;
43 ddr
[all...]
/u-boot/board/freescale/ls1021atsn/
H A Dls1021atsn.c31 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; local
34 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
36 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
37 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
39 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
40 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
41 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
42 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
43 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
44 out_be32(&ddr
[all...]
/u-boot/board/freescale/ls2080ardb/
H A DMakefile6 obj-y += ddr.o
/u-boot/board/freescale/ls1028a/
H A DMakefile8 obj-y += ddr.o
/u-boot/board/gdsys/mpc8308/
H A Dsdram.c45 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
46 out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG);
49 out_be32(&im->ddr.cs_config[1], 0);
51 out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_SDRAM_CLK_CNTL);
52 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3);
53 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1);
54 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2);
55 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0);
57 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG);
58 out_be32(&im->ddr
[all...]
/u-boot/board/freescale/ls1021aiot/
H A Dls1021aiot.c55 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; local
58 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
60 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
61 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
63 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
64 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
65 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
66 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
67 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
68 out_be32(&ddr
[all...]
/u-boot/arch/mips/mach-ath79/ar934x/
H A DMakefile5 obj-y += ddr.o
/u-boot/arch/mips/mach-ath79/ar933x/
H A DMakefile4 obj-y += ddr.o
/u-boot/arch/mips/mach-ath79/qca953x/
H A DMakefile4 obj-y += ddr.o
/u-boot/board/freescale/ls1043aqds/
H A DMakefile7 obj-y += ddr.o
/u-boot/board/freescale/ls1046aqds/
H A DMakefile7 obj-y += ddr.o
/u-boot/board/freescale/ls2080aqds/
H A DMakefile6 obj-y += ddr.o
/u-boot/board/freescale/mpc8548cds/
H A DMakefile8 obj-y += ddr.o
/u-boot/board/freescale/p2041rdb/
H A DMakefile9 obj-y += ddr.o
/u-boot/board/imgtec/boston/
H A DMakefile6 obj-y += ddr.o
/u-boot/board/freescale/ls1046afrwy/
H A DMakefile5 obj-y += ddr.o

Completed in 112 milliseconds

12345678910