Searched refs:con (Results 1 - 25 of 35) sorted by relevance

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/u-boot/drivers/clk/rockchip/
H A D	clk_rk3588.c	136 u32 con, sel, rate; 140 con = readl(&cru->clksel_con[165]); 141 sel = (con & ACLK_CENTER_ROOT_SEL_MASK) >> 153 con = readl(&cru->clksel_con[165]); 154 sel = (con & ACLK_CENTER_LOW_ROOT_SEL_MASK) >> 166 con = readl(&cru->clksel_con[165]); 167 sel = (con & HCLK_CENTER_ROOT_SEL_MASK) >> 179 con = readl(&cru->clksel_con[165]); 180 sel = (con & PCLK_CENTER_ROOT_SEL_MASK) >> 268 u32 con, se 126 u32 con, sel, rate; local 258 u32 con, sel, div, rate, prate; local 355 u32 sel, con; local 464 u32 sel, con; local 549 u32 sel, con; local 628 u32 div, sel, con, prate; local 719 u32 sel, con, div, prate; local 873 u32 div, con, parent; local 922 u32 div, sel, con, parent; local 1036 u32 div, sel, con, parent; local 1088 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; local 1198 u32 con, div; local 1266 u32 reg, con, fracdiv, div, src, p_src, p_rate; local 1403 u32 con, div, src; local 2050 u32 con, div, sel, parent; local [all...]
H A D	clk_rv1126.c	193 u32 div, con; local 197 con = readl(&pmucru->pmu_clksel_con[2]); 198 div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; 201 con = readl(&pmucru->pmu_clksel_con[3]); 202 div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; 240 u32 div, sel, con; local 244 con = readl(&pmucru->pmu_clksel_con[6]); 245 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; 246 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; 251 con 317 u32 div, con; local 345 u32 div, con; local 569 u32 con, div; local 594 u32 con, div, sel, parent; local 688 u32 con, div, parent; local 740 u32 con, div; local 765 u32 div, con; local 827 u32 div, con; local 854 u32 div, sel, con; local 889 u32 div, con; local 913 u32 div, sel, con, parent; local 998 u32 div, sel, con, con_id; local 1079 u32 div, sel, con, parent; local 1111 u32 div, sel, con, parent; local 1143 u32 div, sel, con, parent; local 1176 u32 div, sel, con, parent; local 1239 u32 div, sel, con, parent; local 1272 u32 div, sel, con, parent; local 1305 u32 div, sel, con, parent; local 1338 u32 con, sel, div_sel; local 1367 u32 div, con, parent; local 1380 u32 div, sel, con, parent; local [all...]
H A D	clk_rk3308.c	182 u32 div, con, con_id; local 202 con = readl(&cru->clksel_con[con_id]); 203 div = (con & CLK_I2C_DIV_CON_MASK) >> CLK_I2C_DIV_CON_SHIFT; 246 u32 con = readl(&cru->clksel_con[43]); local 250 if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL0) 253 else if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL1) 292 u32 div, con, con_id; local 308 con = readl(&cru->clksel_con[con_id]); 309 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; 311 if ((con 364 u32 div, con; local 392 u32 div, con; local 420 u32 div, con, con_id; local 479 u32 div, con; local 508 u32 div, pll_sel, con, con_id, parent; local 560 u32 div, pll_sel, vol_sel, con, parent; local 650 u32 div, con, parent = priv->dpll_hz; local 714 u32 div, con, parent = priv->dpll_hz; local 777 u32 div, con, parent = priv->vpll0_hz; local 832 u32 div, con, parent; local 890 u32 con, fracdiv; local [all...]
H A D	clk_rk3568.c	229 u32 div, con; local 233 con = readl(&pmucru->pmu_clksel_con[3]); 234 div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; 268 u32 div, sel, con, parent; local 272 con = readl(&pmucru->pmu_clksel_con[6]); 273 sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; 274 div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; 320 u32 div, con, sel, parent; local 322 con = readl(&pmucru->pmu_clksel_con[2]); 323 sel = (con 601 int div, mask, shift, con; local 656 int div, mask, shift, con; local 716 u32 con, sel, rate; local 797 u32 con, sel, rate; local 876 u32 con, sel, rate; local 1005 u32 sel, con; local 1064 u32 sel, con; local 1141 u32 sel, con; local 1208 u32 div, sel, con, prate; local 1284 u32 sel, con; local 1405 u32 sel, con; local 1503 u32 sel, con; local 1555 u32 sel, con; local 1605 u32 sel, con; local 1669 u32 sel, con; local 1715 u32 div, sel, con, parent; local 1756 u32 conid, div, sel, con, parent; local 1797 u32 i, conid, con, sel, div, best_div = 0, best_sel = 0; local 1875 u32 sel, con; local 1925 u32 sel, con; local 1978 u32 sel, con; local 2031 u32 con, sel, div_sel; local 2062 u32 con, div, p_rate; local 2102 u32 con, div, src, p_rate; local 2188 u32 reg, con, fracdiv, div, src, p_src, p_rate; local [all...]
H A D	clk_px30.c	264 u32 con, shift, mask; local 266 con = readl(mode); 270 switch ((con & mask) >> shift) { 275 con = readl(&pll->con0); 276 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 277 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 278 con = readl(&pll->con1); 279 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 280 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 291 u32 div, con; local 421 u32 con, fracdiv, gate; local 482 u32 div, con; local 514 u32 div, con, con_id; local 586 u32 div, con; local 612 u32 div, con; local 665 u32 div, con; local 691 u32 div, con; local 717 u32 div, con; local 770 u32 div, con, parent; local 867 u32 div, con, parent; local 939 u32 div, con, parent; local 997 u32 div, con, parent; local 1054 u32 con; local 1085 u32 con = readl(&cru->clksel_con[22]); local 1535 u32 div, con; local [all...]
H A D	clk_rk3128.c	245 u32 con; local 259 con = readl(&cru->cru_mode_con); 263 switch ((con & mask) >> shift) { 268 con = readl(&pll->con0); 269 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 270 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 271 con = readl(&pll->con1); 272 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 273 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 286 u32 con; local 351 u32 div, con; local 460 u32 div, con, parent; local [all...]
H A D	clk_rk3066.c	224 u32 con; local 233 con = readl(&cru->cru_mode_con); 235 switch (FIELD_GET(APLL_MODE_MASK, con >> shift)) { 240 con = readl(&pll->con0); 241 no = bitfield_extract_by_mask(con, CLKOD_MASK) + 1; 242 nr = bitfield_extract_by_mask(con, CLKR_MASK) + 1; 243 con = readl(&pll->con1); 244 nf = bitfield_extract_by_mask(con, CLKF_MASK) + 1; 257 u32 con; local 262 con 322 u32 con; local 368 u32 div, con; local [all...]
H A D	clk_rk3036.c	177 uint32_t con; local 191 con = readl(&cru->cru_mode_con); 195 switch ((con & mask) >> shift) { 201 con = readl(&pll->con0); 202 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 203 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 204 con = readl(&pll->con1); 205 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 206 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 219 u32 con; local [all...]
H A D	clk_pll.c	364 u32 con = 0, shift, mask; local 367 con = readl(base + pll->mode_offset); 371 switch ((con & mask) >> shift) { 376 con = readl(base + pll->con_offset); 377 postdiv1 = (con & RK3036_PLLCON0_POSTDIV1_MASK) >> 379 fbdiv = (con & RK3036_PLLCON0_FBDIV_MASK) >> 381 con = readl(base + pll->con_offset + 0x4); 382 postdiv2 = (con & RK3036_PLLCON1_POSTDIV2_MASK) >> 384 refdiv = (con & RK3036_PLLCON1_REFDIV_MASK) >> 386 dsmpd = (con 550 u32 con = 0, shift, mode; local [all...]
H A D	clk_rk3328.c	341 u32 div, con; local 345 con = readl(&cru->clksel_con[34]); 346 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 349 con = readl(&cru->clksel_con[34]); 350 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 353 con = readl(&cru->clksel_con[35]); 354 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 357 con = readl(&cru->clksel_con[35]); 358 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK; 428 u32 con local 452 u32 div, con, con_id; local 517 u32 div, con; local 591 u32 div, con, parent; local 622 u32 con, parent; local 669 u32 div, con; local [all...]
H A D	clk_rk3188.c	233 uint32_t con; local 242 con = readl(&cru->cru_mode_con); 244 switch ((con >> shift) & APLL_MODE_MASK) { 249 con = readl(&pll->con0); 250 no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; 251 nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; 252 con = readl(&pll->con1); 253 nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; 266 u32 con; local 271 con 331 u32 con; local [all...]
H A D	clk_rk3288.c	316 u32 con = readl(&cru->cru_clksel_con[21]); local 320 if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 323 else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) == 547 uint32_t con; local 556 con = readl(&cru->cru_mode_con); 558 switch ((con >> shift) & CRU_MODE_MASK) { 563 con = readl(&pll->con0); 564 no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1; 565 nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1; 566 con 581 u32 con; local 664 u32 con; local [all...]
H A D	clk_rk322x.c	179 uint32_t con; local 193 con = readl(&cru->cru_mode_con); 197 switch ((con & mask) >> shift) { 203 con = readl(&pll->con0); 204 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; 205 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT; 206 con = readl(&pll->con1); 207 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; 208 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; 220 u32 con; local 257 u32 con = readl(&cru->cru_clksel_con[5]); local [all...]
H A D	clk_rv1108.c	150 uint32_t con = readl(&cru->clksel_con[24]); local 154 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL) 175 u32 con = readl(&cru->clksel_con[27]); local 179 if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL) 420 u32 div, con; local 424 con = readl(&cru->clksel_con[19]); 425 div = bitfield_extract(con, CLK_I2C0_DIV_CON_SHIFT, 429 con = readl(&cru->clksel_con[19]); 430 div = bitfield_extract(con, CLK_I2C1_DIV_CON_SHIFT, 434 con 494 u32 div, con; local [all...]
H A D	clk_rk3399.c	510 #define I2C_CLK_DIV_VALUE(con, bus) \ 511 ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK) 521 u32 div, con; local 525 con = readl(&cru->clksel_con[61]); 526 div = I2C_CLK_DIV_VALUE(con, 1); 529 con = readl(&cru->clksel_con[62]); 530 div = I2C_CLK_DIV_VALUE(con, 2); 533 con = readl(&cru->clksel_con[63]); 534 div = I2C_CLK_DIV_VALUE(con, 3); 537 con 728 u32 div, con; local 759 rk3399_dwmmc_set_clk(struct rockchip_cru *cru, unsigned int con, ulong set_rate) argument 1544 u32 div, con; local 1598 u32 div, con; local [all...]
H A D	clk_rk3368.c	70 uint32_t con; local 73 con = readl(&pll->con3); 75 switch ((con & PLL_MODE_MASK) >> PLL_MODE_SHIFT) { 79 con = readl(&pll->con0); 80 no = ((con & PLL_OD_MASK) >> PLL_OD_SHIFT) + 1; 81 nr = ((con & PLL_NR_MASK) >> PLL_NR_SHIFT) + 1; 82 con = readl(&pll->con1); 83 nf = ((con & PLL_NF_MASK) >> PLL_NF_SHIFT) + 1; 164 u32 div, con, con_id, rate; local 181 con 329 u32 con = readl(&cru->clksel_con[43]); local [all...]
/u-boot/test/dm/
H A D	video.c	147 struct udevice *dev, *con; local 155 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); 156 ut_assertok(vidconsole_select_font(con, "8x16", 0)); 159 ut_assertok(uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con)); 160 vidconsole_putc_xy(con, 0, 0, 'a'); 163 vidconsole_putc_xy(con, 0, 0, ' '); 167 vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i); 170 vidconsole_set_row(con, 0, WHITE); 174 vidconsole_putc_xy(con, VID_TO_POS(i * 8), 0, ' ' + i); 183 struct udevice *dev, *con; local 220 struct udevice *dev, *con; local 239 struct udevice *dev, *con; local 282 struct udevice *dev, *con; local 554 struct udevice *dev, *con; local 570 struct udevice *dev, *con; local 591 struct udevice *dev, *con; local [all...]
/u-boot/board/atmel/common/
H A D	video_display.c	31 struct udevice *dev, *con; local 66 ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con); 70 priv = dev_get_uclass_priv(con); 71 vidconsole_position_cursor(con, 0, (logo_info.logo_height + 74 vidconsole_put_char(con, *s);
/u-boot/board/gdsys/mpc8308/
H A D	gazerbeam.c	51 int con = 0; local 65 sysinfo_get_int(sysinfo, BOARD_VARIANT, &con); 76 if (mc == 2 || con == VAR_CON) { 82 if (con == VAR_CON) { 96 int con = 0; local 104 sysinfo_get_int(sysinfo, BOARD_VARIANT, &con); 108 printf("%s", con == VAR_CON ? "CON" : "CPU");
/u-boot/drivers/sysinfo/
H A D	gazerbeam.c	65 int mc4, mc2, sc, mc2_sc, con; local 117 con = dm_gpio_get_value(&priv->var_gpios[CON_GPIO_NO]); 118 if (con < 0) { 119 debug("%s: Error while reading 'con' GPIO (err = %d)", 120 dev->name, con); 121 return con; 124 priv->variant = con ? VAR_CON : VAR_CPU;
/u-boot/board/kosagi/novena/
H A D	novena.c	71 struct udevice *con; local 77 ret = uclass_get_device(UCLASS_VIDEO_CONSOLE, 0, &con); 82 vidconsole_position_cursor(con, 0, 0); 83 vidconsole_put_string(con, buf);
/u-boot/drivers/sound/
H A D	samsung-i2s.c	63 unsigned int con = readl(&i2s_reg->con); local 67 con |= CON_ACTIVE; 68 con &= ~CON_TXCH_PAUSE; 70 con |= CON_TXCH_PAUSE; 71 con &= ~CON_ACTIVE; 75 writel(con, &i2s_reg->con); 282 if (!(CON_TXFIFO_FULL & (readl(&i2s_reg->con)))) { 335 writel(CON_RESET, &i2s_reg->con); [all...]
/u-boot/drivers/i2c/
H A D	rk_i2c.c	88 debug("i2c_con: 0x%08x\n", readl(&regs->con)); 112 writel(I2C_CON_EN | I2C_CON_START, &regs->con); 140 writel(I2C_CON_EN | I2C_CON_STOP, &regs->con); 162 writel(0, &i2c->regs->con); 174 uint con = 0; local 199 con = I2C_CON_EN; 206 con = I2C_CON_EN | I2C_CON_LASTACK; 215 con |= I2C_CON_MOD(I2C_MODE_RX); 217 con |= I2C_CON_MOD(I2C_MODE_TRX); 219 writel(con, [all...]
/u-boot/arch/arm/include/asm/arch-rockchip/
H A D	i2c.h	11 u32 con; member in struct:i2c_regs
/u-boot/include/
H A D	i2s.h	70 unsigned int con; /* base + 0 , Control register */ member in struct:i2s_reg

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Indexes created Thu May 30 22:23:56 MDT 2024