| /u-boot/drivers/video/sunxi/ |
| H A D | tve_common.c | 22 writel(SUNXI_TVE_CFG0_VGA, &tve->cfg0);
34 writel(SUNXI_TVE_CFG0_PAL, &tve->cfg0);
60 writel(SUNXI_TVE_CFG0_NTSC, &tve->cfg0);
|
| /u-boot/arch/mips/mach-mtmips/include/mach/ |
| H A D | ddr.h | 26 u32 cfg0; member in struct:mc_ddr_cfg
|
| /u-boot/arch/arm/mach-imx/ |
| H A D | mmdc_size.c | 21 u32 cfg0; member in struct:esd_mmdc_regs
|
| /u-boot/arch/mips/mach-mtmips/ |
| H A D | ddr_init.c | 85 writel(cfg->cfg0, memc + MEMCTL_DDR_CFG0_REG);
203 static void mc_sdr_init(void __iomem *memc, mc_reset_t mc_reset, u32 cfg0, argument
210 writel(cfg0, memc + MEMCTL_SDRAM_CFG0_REG);
|
| /u-boot/drivers/pci/ |
| H A D | pcie_layerscape_rc.c | 173 *paddress = pcie_rc->cfg0 + offset;
358 pcie_rc->cfg0 = map_physmem(pcie_rc->cfg_res.start,
361 pcie_rc->cfg1 = pcie_rc->cfg0 +
369 debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
371 (unsigned long)pcie->ctrl, (unsigned long)pcie_rc->cfg0,
|
| H A D | pcie_layerscape.h | 157 void __iomem *cfg0; member in struct:ls_pcie_rc
|
| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | tve.h | 29 u32 cfg0; /* 0x004 */ member in struct:sunxi_tve_reg
|
| H A D | dram_sun50i_h616.h | 47 u32 cfg0; /* 0x0 */ member in struct:sunxi_mctl_com_reg::__anon1
|
| H A D | dram_sun50i_h6.h | 52 u32 cfg0; /* 0x0 */ member in struct:sunxi_mctl_com_reg::__anon57
|
| /u-boot/drivers/i2c/ |
| H A D | geni_i2c.c | 358 u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0}; local
386 cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
390 writel(cfg0, geni->base + SE_GENI_TX_PACKING_CFG0);
394 writel(cfg0, geni->base + SE_GENI_RX_PACKING_CFG0);
|
| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | fdt.c | 166 u32 cfg0 = in_be32(&cpc->cpccfg0); local
168 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CFG_SYS_NUM_CPC;
169 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
170 line_size = CPC_CFG0_LINE_SZ(cfg0);
|
| /u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun50i_h6.c | 108 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) local
116 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
117 writel(cfg0, &mctl_com->master[port].cfg0);
|
| H A D | dram_sunxi_dw.c | 95 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) local
103 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
104 writel(cfg0, &mctl_com->mcr[port][0]);
|
| H A D | dram_sun50i_h616.c | 45 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0) local
53 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
54 writel_relaxed(cfg0, &mctl_com->master[port].cfg0);
|
| /u-boot/arch/arm/mach-imx/mx7ulp/ |
| H A D | soc.c | 422 serialnr->low = (fuse->cfg0 & 0xFFFF) + ((fuse->cfg1 & 0xFFFF) << 16);
|
| /u-boot/arch/powerpc/include/asm/ |
| H A D | fsl_liodn.h | 226 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
|
| H A D | immap_85xx.h | 2386 u32 cfg0; /* cfg register 0 */ member in struct:ccsr_raide::__anon57::__anon58
|
| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| H A D | imx-regs.h | 205 u32 cfg0; member in struct:fuse_bank1_regs
|
| /u-boot/arch/mips/mach-octeon/ |
| H A D | octeon_qlm.c | 4587 cvmx_gserx_lanex_tx_cfg_0_t cfg0; local
4593 cfg0.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_TX_CFG_0(l, qlm));
4594 cfg0.s.cfg_tx_swing = 0x12;
4595 csr_wr_node(node, CVMX_GSERX_LANEX_TX_CFG_0(l, qlm), cfg0.u64);
5240 cvmx_gserx_lanex_tx_cfg_0_t cfg0; local
5248 cfg0.u64 = csr_rd(CVMX_GSERX_LANEX_TX_CFG_0(l, qlm));
5249 cfg0.s.cfg_tx_swing = 0x12;
5250 csr_wr(CVMX_GSERX_LANEX_TX_CFG_0(l, qlm), cfg0.u64);
|
| /u-boot/arch/arm/include/asm/arch-mx7ulp/ |
| H A D | imx-regs.h | 1016 u32 cfg0; member in struct:fuse_bank1_regs
|
| /u-boot/arch/arm/include/asm/arch-mx31/ |
| H A D | imx-regs.h | 511 u32 cfg0; member in struct:esdc_regs
|
| /u-boot/arch/arm/include/asm/arch-mx7/ |
| H A D | imx-regs.h | 917 u32 cfg0; member in struct:fuse_bank1_regs
|