1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (C) 2020 MediaTek Inc. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 */ 7 8#ifndef _MTMIPS_DDR_H_ 9#define _MTMIPS_DDR_H_ 10 11#include <linux/io.h> 12#include <linux/types.h> 13 14enum mc_dram_size { 15 DRAM_8MB, 16 DRAM_16MB, 17 DRAM_32MB, 18 DRAM_64MB, 19 DRAM_128MB, 20 DRAM_256MB, 21 22 __DRAM_SZ_MAX 23}; 24 25struct mc_ddr_cfg { 26 u32 cfg0; 27 u32 cfg1; 28 u32 cfg2; 29 u32 cfg3; 30 u32 cfg4; 31}; 32 33typedef void (*mc_reset_t)(int assert); 34 35struct mc_ddr_init_param { 36 void __iomem *memc; 37 38 u32 sdr_cfg0; 39 u32 sdr_cfg1; 40 41 u32 dq_dly; 42 u32 dqs_dly; 43 44 const struct mc_ddr_cfg *cfgs; 45 mc_reset_t mc_reset; 46 47 u32 memsize; 48 u32 bus_width; 49}; 50 51void sdr_init(struct mc_ddr_init_param *param); 52void ddr1_init(struct mc_ddr_init_param *param); 53void ddr2_init(struct mc_ddr_init_param *param); 54void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw); 55 56#endif /* _MTMIPS_DDR_H_ */ 57