1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright 2009-2011 Freescale Semiconductor, Inc. 4 */ 5 6#ifndef _FSL_LIODN_H_ 7#define _FSL_LIODN_H_ 8 9#include <asm/types.h> 10#include <fsl_qbman.h> 11 12struct srio_liodn_id_table { 13 u32 id[2]; 14 unsigned long reg_offset[2]; 15 u8 num_ids; 16 u8 portid; 17}; 18#define SET_SRIO_LIODN_1(port, idA) \ 19 { .id = { idA }, .num_ids = 1, .portid = port, \ 20 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ 21 + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ 22 } 23 24#define SET_SRIO_LIODN_2(port, idA, idB) \ 25 { .id = { idA, idB }, .num_ids = 2, .portid = port, \ 26 .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ 27 + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ 28 .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \ 29 + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ 30 } 31 32#define SET_SRIO_LIODN_BASE(port, id_a) \ 33 { .id = { id_a }, .num_ids = 1, .portid = port, \ 34 .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \ 35 + (port - 1) * 0x200 \ 36 + CFG_SYS_FSL_SRIO_ADDR, \ 37 } 38 39struct liodn_id_table { 40 const char * compat; 41 u32 id[2]; 42 u8 num_ids; 43 phys_addr_t compat_offset; 44 unsigned long reg_offset; 45}; 46 47struct fman_liodn_id_table { 48 /* Freescale FMan Device Tree binding was updated for FMan. 49 * We need to support both new and old compatibles in order not to 50 * break backward compatibility. 51 */ 52 const char *compat[2]; 53 u32 id[2]; 54 u8 num_ids; 55 phys_addr_t compat_offset; 56 unsigned long reg_offset; 57}; 58 59extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid); 60extern void set_liodns(void); 61extern void fdt_fixup_liodn(void *blob); 62 63#define SET_LIODN_BASE_1(idA) \ 64 { .id = { idA }, .num_ids = 1, } 65 66#define SET_LIODN_BASE_2(idA, idB) \ 67 { .id = { idA, idB }, .num_ids = 2 } 68 69#define SET_FMAN_LIODN_ENTRY(name1, name2, idA, off, compatoff)\ 70 { .compat[0] = name1, \ 71 .compat[1] = name2, \ 72 .id = { idA }, .num_ids = 1, \ 73 .reg_offset = off + CFG_SYS_CCSRBAR, \ 74 .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ 75 } 76 77#define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ 78 { .compat = name, \ 79 .id = { idA }, .num_ids = 1, \ 80 .reg_offset = off + CFG_SYS_CCSRBAR, \ 81 .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ 82 } 83 84#define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ 85 { .compat = name, \ 86 .id = { idA, idB }, .num_ids = 2, \ 87 .reg_offset = off + CFG_SYS_CCSRBAR, \ 88 .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ 89 } 90 91#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ 92 SET_LIODN_ENTRY_1(compat, liodn, \ 93 offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \ 94 compatoff) 95 96#define SET_USB_LIODN(usbNum, compat, liodn) \ 97 SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\ 98 CFG_SYS_MPC85xx_USB##usbNum##_OFFSET) 99 100#define SET_SATA_LIODN(sataNum, liodn) \ 101 SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\ 102 CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET) 103 104#define SET_PCI_LIODN(compat, pciNum, liodn) \ 105 SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\ 106 CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) 107 108#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \ 109 SET_LIODN_ENTRY_1(compat, liodn,\ 110 offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\ 111 CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) 112 113/* reg nodes for DMA start @ 0x300 */ 114#define SET_DMA_LIODN(dmaNum, compat, liodn) \ 115 SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\ 116 CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300) 117 118#define SET_SDHC_LIODN(sdhcNum, liodn) \ 119 SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\ 120 CFG_SYS_MPC85xx_ESDHC_OFFSET) 121 122#define SET_QE_LIODN(liodn) \ 123 SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\ 124 CFG_SYS_MPC85xx_QE_OFFSET) 125 126#define SET_TDM_LIODN(liodn) \ 127 SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\ 128 CFG_SYS_MPC85xx_TDM_OFFSET) 129 130#define SET_QMAN_LIODN(liodn) \ 131 SET_LIODN_ENTRY_1("fsl,qman", liodn, \ 132 offsetof(struct ccsr_qman, liodnr) + \ 133 CFG_SYS_FSL_QMAN_OFFSET, \ 134 CFG_SYS_FSL_QMAN_OFFSET) 135 136#define SET_BMAN_LIODN(liodn) \ 137 SET_LIODN_ENTRY_1("fsl,bman", liodn, \ 138 offsetof(struct ccsr_bman, liodnr) + \ 139 CFG_SYS_FSL_BMAN_OFFSET, \ 140 CFG_SYS_FSL_BMAN_OFFSET) 141 142#define SET_PME_LIODN(liodn) \ 143 SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \ 144 CFG_SYS_FSL_CORENET_PME_OFFSET, \ 145 CFG_SYS_FSL_CORENET_PME_OFFSET) 146 147#define SET_PMAN_LIODN(num, liodn) \ 148 SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \ 149 offsetof(struct ccsr_pman, ppa1) + \ 150 CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \ 151 CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET) 152 153/* -1 from portID due to how immap has the registers */ 154#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \ 155 CFG_SYS_FSL_FM##fmNum##_OFFSET + \ 156 offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1]) 157 158#ifdef CONFIG_SYS_FMAN_V3 159/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ 160#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ 161 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \ 162 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ 163 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) 164 165/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ 166#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ 167 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ 168 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ 169 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) 170 171/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */ 172#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \ 173 SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ 174 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ 175 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) 176#else 177/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ 178#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ 179 SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \ 180 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ 181 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) 182 183/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ 184#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ 185 SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \ 186 liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ 187 CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) 188#endif 189/* 190 * handle both old and new versioned SEC properties: 191 * "fsl,secX.Y" became "fsl,sec-vX.Y" during development 192 */ 193#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ 194 SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ 195 offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ 196 CFG_SYS_FSL_SEC_OFFSET, \ 197 CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \ 198 SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ 199 offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ 200 CFG_SYS_FSL_SEC_OFFSET, \ 201 CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) 202 203/* This is a bit evil since we treat rtic param as both a string & hex value */ 204#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ 205 SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ 206 liodnA, \ 207 offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ 208 CFG_SYS_FSL_SEC_OFFSET, \ 209 CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ 210 SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ 211 liodnA, \ 212 offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ 213 CFG_SYS_FSL_SEC_OFFSET, \ 214 CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) 215 216#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ 217 SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ 218 offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ 219 CFG_SYS_FSL_SEC_OFFSET, 0) 220 221#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \ 222 SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \ 223 liodnA, \ 224 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \ 225 CFG_SYS_FSL_RAID_ENGINE_OFFSET, \ 226 offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \ 227 CFG_SYS_FSL_RAID_ENGINE_OFFSET) 228 229#define SET_RMAN_LIODN(ibNum, liodn) \ 230 SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \ 231 offsetof(struct ccsr_rman, mmitdr) + \ 232 CFG_SYS_FSL_CORENET_RMAN_OFFSET, \ 233 CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000) 234 235extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; 236extern struct liodn_id_table raide_liodn_tbl[]; 237extern struct fman_liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; 238#ifdef CONFIG_SYS_SRIO 239extern struct srio_liodn_id_table srio_liodn_tbl[]; 240extern int srio_liodn_tbl_sz; 241#endif 242extern struct liodn_id_table rman_liodn_tbl[]; 243extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz; 244extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz; 245extern int rman_liodn_tbl_sz; 246 247#endif 248