Searched refs:MII_CTRL1000 (Results 1 - 14 of 14) sorted by relevance

/u-boot/board/udoo/
H A Dudoo.c70 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
/u-boot/drivers/net/phy/
H A Dmicrel_ksz90x1.c267 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, ctrl1000);
359 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
468 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0);
H A Drealtek.c145 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
150 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg);
H A Ddp83869.c350 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT);
397 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT);
H A Dphy.c98 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
117 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv);
319 MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
/u-boot/include/linux/
H A Dmii.h22 #define MII_CTRL1000 0x09 /* 1000BASE-T control */ macro
/u-boot/drivers/net/ti/
H A Ddavinci_emac.c348 davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
351 davinci_eth_phy_write(phy_addr, MII_CTRL1000, val);
352 davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
/u-boot/drivers/net/
H A Dravb.c327 reg = phy_read(phydev, -1, MII_CTRL1000);
329 phy_write(phydev, -1, MII_CTRL1000, reg);
H A Dbcm6368-eth.c279 port->phy_id, MII_CTRL1000);
H A Dag7xxx.c900 ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
905 ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000,
/u-boot/cmd/
H A Dmii.c137 { MII_CTRL1000, reg_9_desc_tbl, ARRAY_SIZE(reg_9_desc_tbl),
/u-boot/drivers/usb/eth/
H A Dr8152.h536 #define MII_CTRL1000 0x09 /* 1000BASE-T control */ macro
H A Dasix88179.c354 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv);
H A Dr8152.c1007 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
1061 r8152_mdio_write(tp, MII_CTRL1000, gbcr);

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