1// SPDX-License-Identifier: GPL-2.0 2/* 3 * TI PHY drivers 4 * 5 */ 6 7#include <common.h> 8#include <phy.h> 9#include <linux/compat.h> 10#include <malloc.h> 11 12#include <dm.h> 13#include <dt-bindings/net/ti-dp83869.h> 14 15/* TI DP83869 */ 16#define DP83869_DEVADDR 0x1f 17 18#define MII_DP83869_PHYCTRL 0x10 19#define MII_DP83869_MICR 0x12 20#define MII_DP83869_CFG2 0x14 21#define MII_DP83869_BISCR 0x16 22#define DP83869_CTRL 0x1f 23#define DP83869_CFG4 0x1e 24 25/* Extended Registers */ 26#define DP83869_GEN_CFG3 0x0031 27#define DP83869_RGMIICTL 0x0032 28#define DP83869_STRAP_STS1 0x006E 29#define DP83869_RGMIIDCTL 0x0086 30#define DP83869_IO_MUX_CFG 0x0170 31#define DP83869_OP_MODE 0x01df 32#define DP83869_FX_CTRL 0x0c00 33 34#define DP83869_SW_RESET BIT(15) 35#define DP83869_SW_RESTART BIT(14) 36 37/* MICR Interrupt bits */ 38#define MII_DP83869_MICR_AN_ERR_INT_EN BIT(15) 39#define MII_DP83869_MICR_SPEED_CHNG_INT_EN BIT(14) 40#define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 41#define MII_DP83869_MICR_PAGE_RXD_INT_EN BIT(12) 42#define MII_DP83869_MICR_AUTONEG_COMP_INT_EN BIT(11) 43#define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN BIT(10) 44#define MII_DP83869_MICR_FALSE_CARRIER_INT_EN BIT(8) 45#define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 46#define MII_DP83869_MICR_WOL_INT_EN BIT(3) 47#define MII_DP83869_MICR_XGMII_ERR_INT_EN BIT(2) 48#define MII_DP83869_MICR_POL_CHNG_INT_EN BIT(1) 49#define MII_DP83869_MICR_JABBER_INT_EN BIT(0) 50 51#define MII_DP83869_BMCR_DEFAULT (BMCR_ANENABLE | \ 52 BMCR_FULLDPLX | \ 53 BMCR_SPEED1000) 54 55/* This is the same bit mask as the BMCR so re-use the BMCR default */ 56#define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT 57 58/* CFG1 bits */ 59#define DP83869_CFG1_DEFAULT (ADVERTISE_1000HALF | \ 60 ADVERTISE_1000FULL | \ 61 CTL1000_AS_MASTER) 62 63/* RGMIICTL bits */ 64#define DP83869_RGMII_TX_CLK_DELAY_EN BIT(1) 65#define DP83869_RGMII_RX_CLK_DELAY_EN BIT(0) 66 67/* STRAP_STS1 bits */ 68#define DP83869_STRAP_OP_MODE_MASK GENMASK(2, 0) 69#define DP83869_STRAP_STS1_RESERVED BIT(11) 70#define DP83869_STRAP_MIRROR_ENABLED BIT(12) 71 72/* PHY CTRL bits */ 73#define DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT 12 74#define DP83869_PHYCR_RX_FIFO_DEPTH_MASK GENMASK(13, 12) 75#define DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT 14 76#define DP83869_PHYCR_TX_FIFO_DEPTH_MASK GENMASK(15, 14) 77#define DP83869_PHYCR_RESERVED_MASK BIT(11) 78#define DP83869_PHYCR_MDI_CROSSOVER_SHIFT 5 79#define DP83869_PHYCR_MDI_CROSSOVER_MDIX 2 80#define DP83869_PHY_CTRL_DEFAULT 0x48 81 82/* RGMIIDCTL bits */ 83#define DP83869_RGMII_TX_CLK_DELAY_SHIFT 4 84#define DP83869_CLK_DELAY_STEP 250 85#define DP83869_CLK_DELAY_MIN 250 86#define DP83869_CLK_DELAY_MAX 4000 87#define DP83869_CLK_DELAY_DEFAULT 2000 88 89/* CFG2 bits */ 90#define MII_DP83869_CFG2_SPEEDOPT_10EN 0x0040 91#define MII_DP83869_CFG2_SGMII_AUTONEGEN 0x0080 92#define MII_DP83869_CFG2_SPEEDOPT_ENH 0x0100 93#define MII_DP83869_CFG2_SPEEDOPT_CNT 0x0800 94#define MII_DP83869_CFG2_SPEEDOPT_INTLOW 0x2000 95#define MII_DP83869_CFG2_MASK 0x003F 96 97/* User setting - can be taken from DTS */ 98#define DEFAULT_FIFO_DEPTH DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 99 100/* IO_MUX_CFG bits */ 101#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f 102 103#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0 104#define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f 105#define DP83869_IO_MUX_CFG_CLK_O_DISABLE BIT(6) 106#define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT 8 107#define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK \ 108 GENMASK(0x1f, DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT) 109 110/* CFG3 bits */ 111#define DP83869_CFG3_PORT_MIRROR_EN BIT(0) 112 113/* OP MODE bits */ 114#define DP83869_OP_MODE_MII BIT(5) 115#define DP83869_SGMII_RGMII_BRIDGE BIT(6) 116 117enum { 118 DP83869_PORT_MIRRORING_KEEP, 119 DP83869_PORT_MIRRORING_EN, 120 DP83869_PORT_MIRRORING_DIS, 121}; 122 123struct dp83869_private { 124 int tx_fifo_depth; 125 int rx_fifo_depth; 126 s32 rx_int_delay; 127 s32 tx_int_delay; 128 int io_impedance; 129 int port_mirroring; 130 bool set_clk_output; 131 int clk_output_sel; 132 int mode; 133}; 134 135static int dp83869_readext(struct phy_device *phydev, int addr, int devad, int reg) 136{ 137 return phy_read_mmd(phydev, devad, reg); 138} 139 140static int dp83869_writeext(struct phy_device *phydev, int addr, int devad, int reg, u16 val) 141{ 142 return phy_write_mmd(phydev, devad, reg, val); 143} 144 145static int dp83869_config_port_mirroring(struct phy_device *phydev) 146{ 147 struct dp83869_private *dp83869 = 148 (struct dp83869_private *)phydev->priv; 149 u16 val; 150 151 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_CFG4); 152 153 if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN) 154 val |= DP83869_CFG3_PORT_MIRROR_EN; 155 else 156 val &= ~DP83869_CFG3_PORT_MIRROR_EN; 157 158 phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_CFG4, val); 159 160 return 0; 161} 162 163static int dp83869_set_strapped_mode(struct phy_device *phydev) 164{ 165 struct dp83869_private *dp83869 = phydev->priv; 166 int val; 167 168 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 169 if (val < 0) 170 return val; 171 172 dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK; 173 174 return 0; 175} 176 177/** 178 * dp83869_data_init - Convenience function for setting PHY specific data 179 * 180 * @phydev: the phy_device struct 181 */ 182static int dp83869_of_init(struct phy_device *phydev) 183{ 184 struct dp83869_private * const dp83869 = phydev->priv; 185 int ret; 186 ofnode node; 187 188 node = phy_get_ofnode(phydev); 189 if (!ofnode_valid(node)) 190 return -EINVAL; 191 192 dp83869->io_impedance = -EINVAL; 193 194 /* Optional configuration, set to default if required */ 195 dp83869->clk_output_sel = ofnode_read_u32_default(node, "ti,clk-output-sel", 196 DP83869_CLK_O_SEL_CHN_A_RCLK); 197 198 if (dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK && 199 dp83869->clk_output_sel != DP83869_CLK_O_SEL_OFF) 200 dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK; 201 202 /* If operation mode is not set use setting from straps */ 203 ret = ofnode_read_s32(node, "ti,op-mode", &dp83869->mode); 204 if (ret == 0) { 205 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 206 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 207 return -EINVAL; 208 } else { 209 ret = dp83869_set_strapped_mode(phydev); 210 if (ret) 211 return ret; 212 } 213 214 if (ofnode_read_bool(node, "ti,max-output-impedance")) 215 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX; 216 else if (ofnode_read_bool(node, "ti,min-output-impedance")) 217 dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN; 218 219 if (ofnode_read_bool(node, "enet-phy-lane-swap")) { 220 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 221 } else { 222 ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1); 223 224 if (ret < 0) 225 return ret; 226 227 if (ret & DP83869_STRAP_MIRROR_ENABLED) 228 dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN; 229 else 230 dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS; 231 } 232 233 dp83869->rx_fifo_depth = ofnode_read_s32_default(node, "rx-fifo-depth", 234 DP83869_PHYCR_FIFO_DEPTH_4_B_NIB); 235 236 dp83869->tx_fifo_depth = ofnode_read_s32_default(node, "tx-fifo-depth", 237 DP83869_PHYCR_FIFO_DEPTH_4_B_NIB); 238 239 /* Internal clock delay values can be configured in steps of 240 * 250ps (0.25ns). The register field for clock delay is 4-bits wide, 241 * the values range from 0b0000 for 0.25ns to 0b1111 for 4ns. 242 */ 243 244 /* RX delay *must* be specified if internal delay of RX is used. */ 245 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 246 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 247 dp83869->rx_int_delay = ofnode_read_u32_default(node, 248 "rx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT); 249 if (dp83869->rx_int_delay > DP83869_CLK_DELAY_MAX || 250 dp83869->rx_int_delay < DP83869_CLK_DELAY_MIN || 251 dp83869->rx_int_delay % DP83869_CLK_DELAY_STEP) { 252 dp83869->rx_int_delay = DP83869_CLK_DELAY_DEFAULT; 253 pr_warn("rx-internal-delay-ps not set/invalid, default" 254 " to %ups\n", DP83869_CLK_DELAY_DEFAULT); 255 } 256 257 dp83869->rx_int_delay = 258 (dp83869->rx_int_delay - DP83869_CLK_DELAY_STEP) 259 / DP83869_CLK_DELAY_STEP; 260 } 261 262 /* TX delay *must* be specified if internal delay of TX is used. */ 263 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 264 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 265 dp83869->tx_int_delay = ofnode_read_u32_default(node, 266 "tx-internal-delay-ps", DP83869_CLK_DELAY_DEFAULT); 267 if (dp83869->tx_int_delay > DP83869_CLK_DELAY_MAX || 268 dp83869->tx_int_delay < DP83869_CLK_DELAY_MIN || 269 dp83869->tx_int_delay % DP83869_CLK_DELAY_STEP) { 270 dp83869->tx_int_delay = DP83869_CLK_DELAY_DEFAULT; 271 pr_warn("tx-internal-delay-ps not set/invalid, default" 272 " to %ups\n", DP83869_CLK_DELAY_DEFAULT); 273 } 274 275 dp83869->tx_int_delay = 276 (dp83869->tx_int_delay - DP83869_CLK_DELAY_STEP) 277 / DP83869_CLK_DELAY_STEP; 278 } 279 280 return 0; 281} 282 283static int dp83869_configure_rgmii(struct phy_device *phydev, 284 struct dp83869_private *dp83869) 285{ 286 int ret = 0, val; 287 288 if (phy_interface_is_rgmii(phydev)) { 289 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL); 290 if (val < 0) 291 return val; 292 293 val &= ~(DP83869_PHYCR_TX_FIFO_DEPTH_MASK | DP83869_PHYCR_RX_FIFO_DEPTH_MASK); 294 val |= (dp83869->tx_fifo_depth << DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT); 295 val |= (dp83869->rx_fifo_depth << DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT); 296 297 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, val); 298 if (ret) 299 return ret; 300 } 301 302 if (dp83869->io_impedance >= 0) { 303 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG); 304 305 val &= ~DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL; 306 val |= dp83869->io_impedance & DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL; 307 308 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val); 309 310 if (ret) 311 return ret; 312 } 313 314 return ret; 315} 316 317static int dp83869_configure_mode(struct phy_device *phydev, 318 struct dp83869_private *dp83869) 319{ 320 int phy_ctrl_val; 321 int ret, val; 322 323 if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET || 324 dp83869->mode > DP83869_SGMII_COPPER_ETHERNET) 325 return -EINVAL; 326 327 /* Below init sequence for each operational mode is defined in 328 * section 9.4.8 of the datasheet. 329 */ 330 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, 331 dp83869->mode); 332 if (ret) 333 return ret; 334 335 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, MII_DP83869_BMCR_DEFAULT); 336 if (ret) 337 return ret; 338 339 phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_PHYCR_RX_FIFO_DEPTH_SHIFT | 340 dp83869->tx_fifo_depth << DP83869_PHYCR_TX_FIFO_DEPTH_SHIFT | 341 DP83869_PHY_CTRL_DEFAULT); 342 343 switch (dp83869->mode) { 344 case DP83869_RGMII_COPPER_ETHERNET: 345 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, 346 phy_ctrl_val); 347 if (ret) 348 return ret; 349 350 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT); 351 if (ret) 352 return ret; 353 354 ret = dp83869_configure_rgmii(phydev, dp83869); 355 if (ret) 356 return ret; 357 break; 358 case DP83869_RGMII_SGMII_BRIDGE: 359 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE); 360 361 val |= DP83869_SGMII_RGMII_BRIDGE; 362 363 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE, val); 364 365 if (ret) 366 return ret; 367 368 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 369 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 370 if (ret) 371 return ret; 372 373 break; 374 case DP83869_1000M_MEDIA_CONVERT: 375 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, 376 phy_ctrl_val); 377 if (ret) 378 return ret; 379 380 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 381 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 382 if (ret) 383 return ret; 384 break; 385 case DP83869_100M_MEDIA_CONVERT: 386 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, 387 phy_ctrl_val); 388 if (ret) 389 return ret; 390 break; 391 case DP83869_SGMII_COPPER_ETHERNET: 392 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83869_PHYCTRL, 393 phy_ctrl_val); 394 if (ret) 395 return ret; 396 397 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, DP83869_CFG1_DEFAULT); 398 if (ret) 399 return ret; 400 401 ret = phy_write_mmd(phydev, DP83869_DEVADDR, 402 DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT); 403 if (ret) 404 return ret; 405 406 break; 407 default: 408 return -EINVAL; 409 } 410 411 return ret; 412} 413 414static int dp83869_config(struct phy_device *phydev) 415{ 416 struct dp83869_private *dp83869; 417 unsigned int val; 418 int ret; 419 420 dp83869 = (struct dp83869_private *)phydev->priv; 421 422 ret = dp83869_of_init(phydev); 423 if (ret) 424 return ret; 425 426 ret = dp83869_configure_mode(phydev, dp83869); 427 if (ret) 428 return ret; 429 430 if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP) 431 dp83869_config_port_mirroring(phydev); 432 433 /* Clock output selection if muxing property is set */ 434 if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK) { 435 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG); 436 437 val &= ~DP83869_IO_MUX_CFG_CLK_O_SEL_MASK; 438 val |= dp83869->clk_output_sel << DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT; 439 440 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_IO_MUX_CFG, val); 441 442 if (ret) 443 return ret; 444 } 445 446 if (phy_interface_is_rgmii(phydev)) { 447 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL, 448 dp83869->rx_int_delay | 449 dp83869->tx_int_delay << DP83869_RGMII_TX_CLK_DELAY_SHIFT); 450 if (ret) 451 return ret; 452 453 val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL); 454 val |= (DP83869_RGMII_TX_CLK_DELAY_EN | 455 DP83869_RGMII_RX_CLK_DELAY_EN); 456 457 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 458 val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN | 459 DP83869_RGMII_RX_CLK_DELAY_EN); 460 461 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 462 val &= ~DP83869_RGMII_TX_CLK_DELAY_EN; 463 464 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 465 val &= ~DP83869_RGMII_RX_CLK_DELAY_EN; 466 467 ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL, 468 val); 469 } 470 471 genphy_config_aneg(phydev); 472 return 0; 473} 474 475static int dp83869_probe(struct phy_device *phydev) 476{ 477 struct dp83869_private *dp83869; 478 479 dp83869 = kzalloc(sizeof(*dp83869), GFP_KERNEL); 480 if (!dp83869) 481 return -ENOMEM; 482 483 phydev->priv = dp83869; 484 return 0; 485} 486 487U_BOOT_PHY_DRIVER(dp83869) = { 488 .name = "TI DP83869", 489 .uid = 0x2000a0f1, 490 .mask = 0xfffffff0, 491 .features = PHY_GBIT_FEATURES, 492 .probe = dp83869_probe, 493 .config = &dp83869_config, 494 .startup = &genphy_startup, 495 .shutdown = &genphy_shutdown, 496 .readext = dp83869_readext, 497 .writeext = dp83869_writeext 498}; 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