1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2014 Rene Griessl <rgriessl@cit-ec.uni-bielefeld.de> 4 * based on the U-Boot Asix driver as well as information 5 * from the Linux AX88179_178a driver 6 */ 7 8#include <common.h> 9#include <dm.h> 10#include <log.h> 11#include <usb.h> 12#include <net.h> 13#include <linux/delay.h> 14#include <linux/mii.h> 15#include "usb_ether.h" 16#include <malloc.h> 17#include <memalign.h> 18#include <errno.h> 19 20/* ASIX AX88179 based USB 3.0 Ethernet Devices */ 21#define AX88179_PHY_ID 0x03 22#define AX_EEPROM_LEN 0x100 23#define AX88179_EEPROM_MAGIC 0x17900b95 24#define AX_MCAST_FLTSIZE 8 25#define AX_MAX_MCAST 64 26#define AX_INT_PPLS_LINK (1 << 16) 27#define AX_RXHDR_L4_TYPE_MASK 0x1c 28#define AX_RXHDR_L4_TYPE_UDP 4 29#define AX_RXHDR_L4_TYPE_TCP 16 30#define AX_RXHDR_L3CSUM_ERR 2 31#define AX_RXHDR_L4CSUM_ERR 1 32#define AX_RXHDR_CRC_ERR (1 << 29) 33#define AX_RXHDR_DROP_ERR (1 << 31) 34#define AX_ENDPOINT_INT 0x01 35#define AX_ENDPOINT_IN 0x02 36#define AX_ENDPOINT_OUT 0x03 37#define AX_ACCESS_MAC 0x01 38#define AX_ACCESS_PHY 0x02 39#define AX_ACCESS_EEPROM 0x04 40#define AX_ACCESS_EFUS 0x05 41#define AX_PAUSE_WATERLVL_HIGH 0x54 42#define AX_PAUSE_WATERLVL_LOW 0x55 43 44#define PHYSICAL_LINK_STATUS 0x02 45 #define AX_USB_SS (1 << 2) 46 #define AX_USB_HS (1 << 1) 47 48#define GENERAL_STATUS 0x03 49 #define AX_SECLD (1 << 2) 50 51#define AX_SROM_ADDR 0x07 52#define AX_SROM_CMD 0x0a 53 #define EEP_RD (1 << 2) 54 #define EEP_BUSY (1 << 4) 55 56#define AX_SROM_DATA_LOW 0x08 57#define AX_SROM_DATA_HIGH 0x09 58 59#define AX_RX_CTL 0x0b 60 #define AX_RX_CTL_DROPCRCERR (1 << 8) 61 #define AX_RX_CTL_IPE (1 << 9) 62 #define AX_RX_CTL_START (1 << 7) 63 #define AX_RX_CTL_AP (1 << 5) 64 #define AX_RX_CTL_AM (1 << 4) 65 #define AX_RX_CTL_AB (1 << 3) 66 #define AX_RX_CTL_AMALL (1 << 1) 67 #define AX_RX_CTL_PRO (1 << 0) 68 #define AX_RX_CTL_STOP 0 69 70#define AX_NODE_ID 0x10 71#define AX_MULFLTARY 0x16 72 73#define AX_MEDIUM_STATUS_MODE 0x22 74 #define AX_MEDIUM_GIGAMODE (1 << 0) 75 #define AX_MEDIUM_FULL_DUPLEX (1 << 1) 76 #define AX_MEDIUM_EN_125MHZ (1 << 3) 77 #define AX_MEDIUM_RXFLOW_CTRLEN (1 << 4) 78 #define AX_MEDIUM_TXFLOW_CTRLEN (1 << 5) 79 #define AX_MEDIUM_RECEIVE_EN (1 << 8) 80 #define AX_MEDIUM_PS (1 << 9) 81 #define AX_MEDIUM_JUMBO_EN 0x8040 82 83#define AX_MONITOR_MOD 0x24 84 #define AX_MONITOR_MODE_RWLC (1 << 1) 85 #define AX_MONITOR_MODE_RWMP (1 << 2) 86 #define AX_MONITOR_MODE_PMEPOL (1 << 5) 87 #define AX_MONITOR_MODE_PMETYPE (1 << 6) 88 89#define AX_GPIO_CTRL 0x25 90 #define AX_GPIO_CTRL_GPIO3EN (1 << 7) 91 #define AX_GPIO_CTRL_GPIO2EN (1 << 6) 92 #define AX_GPIO_CTRL_GPIO1EN (1 << 5) 93 94#define AX_PHYPWR_RSTCTL 0x26 95 #define AX_PHYPWR_RSTCTL_BZ (1 << 4) 96 #define AX_PHYPWR_RSTCTL_IPRL (1 << 5) 97 #define AX_PHYPWR_RSTCTL_AT (1 << 12) 98 99#define AX_RX_BULKIN_QCTRL 0x2e 100#define AX_CLK_SELECT 0x33 101 #define AX_CLK_SELECT_BCS (1 << 0) 102 #define AX_CLK_SELECT_ACS (1 << 1) 103 #define AX_CLK_SELECT_ULR (1 << 3) 104 105#define AX_RXCOE_CTL 0x34 106 #define AX_RXCOE_IP (1 << 0) 107 #define AX_RXCOE_TCP (1 << 1) 108 #define AX_RXCOE_UDP (1 << 2) 109 #define AX_RXCOE_TCPV6 (1 << 5) 110 #define AX_RXCOE_UDPV6 (1 << 6) 111 112#define AX_TXCOE_CTL 0x35 113 #define AX_TXCOE_IP (1 << 0) 114 #define AX_TXCOE_TCP (1 << 1) 115 #define AX_TXCOE_UDP (1 << 2) 116 #define AX_TXCOE_TCPV6 (1 << 5) 117 #define AX_TXCOE_UDPV6 (1 << 6) 118 119#define AX_LEDCTRL 0x73 120 121#define GMII_PHY_PHYSR 0x11 122 #define GMII_PHY_PHYSR_SMASK 0xc000 123 #define GMII_PHY_PHYSR_GIGA (1 << 15) 124 #define GMII_PHY_PHYSR_100 (1 << 14) 125 #define GMII_PHY_PHYSR_FULL (1 << 13) 126 #define GMII_PHY_PHYSR_LINK (1 << 10) 127 128#define GMII_LED_ACT 0x1a 129 #define GMII_LED_ACTIVE_MASK 0xff8f 130 #define GMII_LED0_ACTIVE (1 << 4) 131 #define GMII_LED1_ACTIVE (1 << 5) 132 #define GMII_LED2_ACTIVE (1 << 6) 133 134#define GMII_LED_LINK 0x1c 135 #define GMII_LED_LINK_MASK 0xf888 136 #define GMII_LED0_LINK_10 (1 << 0) 137 #define GMII_LED0_LINK_100 (1 << 1) 138 #define GMII_LED0_LINK_1000 (1 << 2) 139 #define GMII_LED1_LINK_10 (1 << 4) 140 #define GMII_LED1_LINK_100 (1 << 5) 141 #define GMII_LED1_LINK_1000 (1 << 6) 142 #define GMII_LED2_LINK_10 (1 << 8) 143 #define GMII_LED2_LINK_100 (1 << 9) 144 #define GMII_LED2_LINK_1000 (1 << 10) 145 #define LED0_ACTIVE (1 << 0) 146 #define LED0_LINK_10 (1 << 1) 147 #define LED0_LINK_100 (1 << 2) 148 #define LED0_LINK_1000 (1 << 3) 149 #define LED0_FD (1 << 4) 150 #define LED0_USB3_MASK 0x001f 151 #define LED1_ACTIVE (1 << 5) 152 #define LED1_LINK_10 (1 << 6) 153 #define LED1_LINK_100 (1 << 7) 154 #define LED1_LINK_1000 (1 << 8) 155 #define LED1_FD (1 << 9) 156 #define LED1_USB3_MASK 0x03e0 157 #define LED2_ACTIVE (1 << 10) 158 #define LED2_LINK_1000 (1 << 13) 159 #define LED2_LINK_100 (1 << 12) 160 #define LED2_LINK_10 (1 << 11) 161 #define LED2_FD (1 << 14) 162 #define LED_VALID (1 << 15) 163 #define LED2_USB3_MASK 0x7c00 164 165#define GMII_PHYPAGE 0x1e 166#define GMII_PHY_PAGE_SELECT 0x1f 167 #define GMII_PHY_PGSEL_EXT 0x0007 168 #define GMII_PHY_PGSEL_PAGE0 0x0000 169 170/* local defines */ 171#define ASIX_BASE_NAME "axg" 172#define USB_CTRL_SET_TIMEOUT 5000 173#define USB_CTRL_GET_TIMEOUT 5000 174#define USB_BULK_SEND_TIMEOUT 5000 175#define USB_BULK_RECV_TIMEOUT 5000 176 177#define AX_RX_URB_SIZE 1024 * 0x12 178#define BLK_FRAME_SIZE 0x200 179#define PHY_CONNECT_TIMEOUT 5000 180 181#define TIMEOUT_RESOLUTION 50 /* ms */ 182 183#define FLAG_NONE 0 184#define FLAG_TYPE_AX88179 (1U << 0) 185#define FLAG_TYPE_AX88178a (1U << 1) 186#define FLAG_TYPE_DLINK_DUB1312 (1U << 2) 187#define FLAG_TYPE_SITECOM (1U << 3) 188#define FLAG_TYPE_SAMSUNG (1U << 4) 189#define FLAG_TYPE_LENOVO (1U << 5) 190#define FLAG_TYPE_GX3 (1U << 6) 191 192/* local vars */ 193static const struct { 194 unsigned char ctrl, timer_l, timer_h, size, ifg; 195} AX88179_BULKIN_SIZE[] = { 196 {7, 0x4f, 0, 0x02, 0xff}, 197 {7, 0x20, 3, 0x03, 0xff}, 198 {7, 0xae, 7, 0x04, 0xff}, 199 {7, 0xcc, 0x4c, 0x04, 8}, 200}; 201 202/* driver private */ 203struct asix_private { 204 struct ueth_data ueth; 205 unsigned pkt_cnt; 206 uint8_t *pkt_data; 207 uint32_t *pkt_hdr; 208 int flags; 209 int rx_urb_size; 210 int maxpacketsize; 211}; 212 213/* 214 * Asix infrastructure commands 215 */ 216static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 217 u16 size, void *data) 218{ 219 int len; 220 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 221 222 debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 223 cmd, value, index, size); 224 225 memcpy(buf, data, size); 226 227 len = usb_control_msg( 228 dev->pusb_dev, 229 usb_sndctrlpipe(dev->pusb_dev, 0), 230 cmd, 231 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 232 value, 233 index, 234 buf, 235 size, 236 USB_CTRL_SET_TIMEOUT); 237 238 return len == size ? 0 : ECOMM; 239} 240 241static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, 242 u16 size, void *data) 243{ 244 int len; 245 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buf, size); 246 247 debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n", 248 cmd, value, index, size); 249 250 len = usb_control_msg( 251 dev->pusb_dev, 252 usb_rcvctrlpipe(dev->pusb_dev, 0), 253 cmd, 254 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 255 value, 256 index, 257 buf, 258 size, 259 USB_CTRL_GET_TIMEOUT); 260 261 memcpy(data, buf, size); 262 263 return len == size ? 0 : ECOMM; 264} 265 266static int asix_read_mac(struct ueth_data *dev, uint8_t *enetaddr) 267{ 268 int ret; 269 270 ret = asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, enetaddr); 271 if (ret < 0) 272 debug("Failed to read MAC address: %02x\n", ret); 273 274 return ret; 275} 276 277static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr) 278{ 279 int ret; 280 281 ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, 282 ETH_ALEN, enetaddr); 283 if (ret < 0) 284 debug("Failed to set MAC address: %02x\n", ret); 285 286 return ret; 287} 288 289static int asix_basic_reset(struct ueth_data *dev, 290 struct asix_private *dev_priv) 291{ 292 u8 buf[5]; 293 u16 *tmp16; 294 u8 *tmp; 295 296 tmp16 = (u16 *)buf; 297 tmp = (u8 *)buf; 298 299 /* Power up ethernet PHY */ 300 *tmp16 = 0; 301 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 302 303 *tmp16 = AX_PHYPWR_RSTCTL_IPRL; 304 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16); 305 mdelay(200); 306 307 *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS; 308 asix_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp); 309 mdelay(200); 310 311 /* RX bulk configuration */ 312 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 313 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 314 315 dev_priv->rx_urb_size = 128 * 20; 316 317 /* Water Level configuration */ 318 *tmp = 0x34; 319 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp); 320 321 *tmp = 0x52; 322 asix_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH, 1, 1, tmp); 323 324 /* Enable checksum offload */ 325 *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP | 326 AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6; 327 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp); 328 329 *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP | 330 AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6; 331 asix_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp); 332 333 /* Configure RX control register => start operation */ 334 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 335 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 336 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16); 337 338 *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL | 339 AX_MONITOR_MODE_RWMP; 340 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp); 341 342 /* Configure default medium type => giga */ 343 *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 344 AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX | 345 AX_MEDIUM_GIGAMODE | AX_MEDIUM_JUMBO_EN; 346 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 2, 2, tmp16); 347 348 u16 adv = 0; 349 adv = ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_LPACK | 350 ADVERTISE_NPAGE | ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP; 351 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_ADVERTISE, 2, &adv); 352 353 adv = ADVERTISE_1000FULL; 354 asix_write_cmd(dev, AX_ACCESS_PHY, 0x03, MII_CTRL1000, 2, &adv); 355 356 return 0; 357} 358 359static int asix_wait_link(struct ueth_data *dev) 360{ 361 int timeout = 0; 362 int link_detected; 363 u8 buf[2]; 364 u16 *tmp16; 365 366 tmp16 = (u16 *)buf; 367 368 do { 369 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 370 MII_BMSR, 2, buf); 371 link_detected = *tmp16 & BMSR_LSTATUS; 372 if (!link_detected) { 373 if (timeout == 0) 374 printf("Waiting for Ethernet connection... "); 375 mdelay(TIMEOUT_RESOLUTION); 376 timeout += TIMEOUT_RESOLUTION; 377 } 378 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 379 380 if (link_detected) { 381 if (timeout > 0) 382 printf("done.\n"); 383 return 0; 384 } else { 385 printf("unable to connect.\n"); 386 return -ENETUNREACH; 387 } 388} 389 390static int asix_init_common(struct ueth_data *dev, 391 struct asix_private *dev_priv) 392{ 393 u8 buf[2], tmp[5], link_sts; 394 u16 *tmp16, mode; 395 396 397 tmp16 = (u16 *)buf; 398 399 debug("** %s()\n", __func__); 400 401 /* Configure RX control register => start operation */ 402 *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START | 403 AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB; 404 if (asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16) != 0) 405 goto out_err; 406 407 if (asix_wait_link(dev) != 0) { 408 /*reset device and try again*/ 409 printf("Reset Ethernet Device\n"); 410 asix_basic_reset(dev, dev_priv); 411 if (asix_wait_link(dev) != 0) 412 goto out_err; 413 } 414 415 /* Configure link */ 416 mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN | 417 AX_MEDIUM_RXFLOW_CTRLEN; 418 419 asix_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS, 420 1, 1, &link_sts); 421 422 asix_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID, 423 GMII_PHY_PHYSR, 2, tmp16); 424 425 if (!(*tmp16 & GMII_PHY_PHYSR_LINK)) { 426 return 0; 427 } else if (GMII_PHY_PHYSR_GIGA == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 428 mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ | 429 AX_MEDIUM_JUMBO_EN; 430 431 if (link_sts & AX_USB_SS) 432 memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5); 433 else if (link_sts & AX_USB_HS) 434 memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5); 435 else 436 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 437 } else if (GMII_PHY_PHYSR_100 == (*tmp16 & GMII_PHY_PHYSR_SMASK)) { 438 mode |= AX_MEDIUM_PS; 439 440 if (link_sts & (AX_USB_SS | AX_USB_HS)) 441 memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5); 442 else 443 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 444 } else { 445 memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5); 446 } 447 448 /* RX bulk configuration */ 449 asix_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp); 450 451 dev_priv->rx_urb_size = (1024 * (tmp[3] + 2)); 452 if (*tmp16 & GMII_PHY_PHYSR_FULL) 453 mode |= AX_MEDIUM_FULL_DUPLEX; 454 asix_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE, 455 2, 2, &mode); 456 457 return 0; 458out_err: 459 return -1; 460} 461 462static int asix_send_common(struct ueth_data *dev, 463 struct asix_private *dev_priv, 464 void *packet, int length) 465{ 466 int err; 467 u32 packet_len, tx_hdr2; 468 int actual_len, framesize; 469 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg, 470 PKTSIZE + (2 * sizeof(packet_len))); 471 472 debug("** %s(), len %d\n", __func__, length); 473 474 packet_len = length; 475 cpu_to_le32s(&packet_len); 476 477 memcpy(msg, &packet_len, sizeof(packet_len)); 478 framesize = dev_priv->maxpacketsize; 479 tx_hdr2 = 0; 480 if (((length + 8) % framesize) == 0) 481 tx_hdr2 |= 0x80008000; /* Enable padding */ 482 483 cpu_to_le32s(&tx_hdr2); 484 485 memcpy(msg + sizeof(packet_len), &tx_hdr2, sizeof(tx_hdr2)); 486 487 memcpy(msg + sizeof(packet_len) + sizeof(tx_hdr2), 488 (void *)packet, length); 489 490 err = usb_bulk_msg(dev->pusb_dev, 491 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), 492 (void *)msg, 493 length + sizeof(packet_len) + sizeof(tx_hdr2), 494 &actual_len, 495 USB_BULK_SEND_TIMEOUT); 496 debug("Tx: len = %zu, actual = %u, err = %d\n", 497 length + sizeof(packet_len), actual_len, err); 498 499 return err; 500} 501 502static int ax88179_eth_start(struct udevice *dev) 503{ 504 struct asix_private *priv = dev_get_priv(dev); 505 506 return asix_init_common(&priv->ueth, priv); 507} 508 509void ax88179_eth_stop(struct udevice *dev) 510{ 511 struct asix_private *priv = dev_get_priv(dev); 512 struct ueth_data *ueth = &priv->ueth; 513 514 debug("** %s()\n", __func__); 515 516 usb_ether_advance_rxbuf(ueth, -1); 517 priv->pkt_cnt = 0; 518 priv->pkt_data = NULL; 519 priv->pkt_hdr = NULL; 520} 521 522int ax88179_eth_send(struct udevice *dev, void *packet, int length) 523{ 524 struct asix_private *priv = dev_get_priv(dev); 525 526 return asix_send_common(&priv->ueth, priv, packet, length); 527} 528 529int ax88179_eth_recv(struct udevice *dev, int flags, uchar **packetp) 530{ 531 struct asix_private *priv = dev_get_priv(dev); 532 struct ueth_data *ueth = &priv->ueth; 533 int ret, len; 534 u16 pkt_len; 535 536 /* No packet left, get a new one */ 537 if (priv->pkt_cnt == 0) { 538 uint8_t *ptr; 539 u16 pkt_cnt; 540 u16 hdr_off; 541 u32 rx_hdr; 542 543 len = usb_ether_get_rx_bytes(ueth, &ptr); 544 debug("%s: first try, len=%d\n", __func__, len); 545 if (!len) { 546 if (!(flags & ETH_RECV_CHECK_DEVICE)) 547 return -EAGAIN; 548 549 ret = usb_ether_receive(ueth, priv->rx_urb_size); 550 if (ret < 0) 551 return ret; 552 553 len = usb_ether_get_rx_bytes(ueth, &ptr); 554 debug("%s: second try, len=%d\n", __func__, len); 555 } 556 557 if (len < 4) { 558 usb_ether_advance_rxbuf(ueth, -1); 559 return -EMSGSIZE; 560 } 561 562 rx_hdr = *(u32 *)(ptr + len - 4); 563 le32_to_cpus(&rx_hdr); 564 565 pkt_cnt = (u16)rx_hdr; 566 if (pkt_cnt == 0) { 567 usb_ether_advance_rxbuf(ueth, -1); 568 return 0; 569 } 570 571 hdr_off = (u16)(rx_hdr >> 16); 572 if (hdr_off > len - 4) { 573 usb_ether_advance_rxbuf(ueth, -1); 574 return -EIO; 575 } 576 577 priv->pkt_cnt = pkt_cnt; 578 priv->pkt_data = ptr; 579 priv->pkt_hdr = (u32 *)(ptr + hdr_off); 580 debug("%s: %d packets received, pkt header at %d\n", 581 __func__, (int)priv->pkt_cnt, (int)hdr_off); 582 } 583 584 le32_to_cpus(priv->pkt_hdr); 585 pkt_len = (*priv->pkt_hdr >> 16) & 0x1fff; 586 587 *packetp = priv->pkt_data + 2; 588 589 priv->pkt_data += (pkt_len + 7) & 0xFFF8; 590 priv->pkt_cnt--; 591 priv->pkt_hdr++; 592 593 debug("%s: return packet of %d bytes (%d packets left)\n", 594 __func__, (int)pkt_len, priv->pkt_cnt); 595 return pkt_len; 596} 597 598static int ax88179_free_pkt(struct udevice *dev, uchar *packet, int packet_len) 599{ 600 struct asix_private *priv = dev_get_priv(dev); 601 struct ueth_data *ueth = &priv->ueth; 602 603 if (priv->pkt_cnt == 0) 604 usb_ether_advance_rxbuf(ueth, -1); 605 606 return 0; 607} 608 609int ax88179_write_hwaddr(struct udevice *dev) 610{ 611 struct eth_pdata *pdata = dev_get_plat(dev); 612 struct asix_private *priv = dev_get_priv(dev); 613 struct ueth_data *ueth = &priv->ueth; 614 615 return asix_write_mac(ueth, pdata->enetaddr); 616} 617 618static int ax88179_eth_probe(struct udevice *dev) 619{ 620 struct eth_pdata *pdata = dev_get_plat(dev); 621 struct asix_private *priv = dev_get_priv(dev); 622 struct usb_device *usb_dev; 623 int ret; 624 625 priv->flags = dev->driver_data; 626 ret = usb_ether_register(dev, &priv->ueth, AX_RX_URB_SIZE); 627 if (ret) 628 return ret; 629 630 usb_dev = priv->ueth.pusb_dev; 631 priv->maxpacketsize = usb_dev->epmaxpacketout[AX_ENDPOINT_OUT]; 632 633 /* Get the MAC address */ 634 ret = asix_read_mac(&priv->ueth, pdata->enetaddr); 635 if (ret) 636 return ret; 637 debug("MAC %pM\n", pdata->enetaddr); 638 639 return 0; 640} 641 642static const struct eth_ops ax88179_eth_ops = { 643 .start = ax88179_eth_start, 644 .send = ax88179_eth_send, 645 .recv = ax88179_eth_recv, 646 .free_pkt = ax88179_free_pkt, 647 .stop = ax88179_eth_stop, 648 .write_hwaddr = ax88179_write_hwaddr, 649}; 650 651U_BOOT_DRIVER(ax88179_eth) = { 652 .name = "ax88179_eth", 653 .id = UCLASS_ETH, 654 .probe = ax88179_eth_probe, 655 .ops = &ax88179_eth_ops, 656 .priv_auto = sizeof(struct asix_private), 657 .plat_auto = sizeof(struct eth_pdata), 658}; 659 660static const struct usb_device_id ax88179_eth_id_table[] = { 661 { USB_DEVICE(0x0b95, 0x1790), .driver_info = FLAG_TYPE_AX88179 }, 662 { USB_DEVICE(0x0b95, 0x178a), .driver_info = FLAG_TYPE_AX88178a }, 663 { USB_DEVICE(0x2001, 0x4a00), .driver_info = FLAG_TYPE_DLINK_DUB1312 }, 664 { USB_DEVICE(0x0df6, 0x0072), .driver_info = FLAG_TYPE_SITECOM }, 665 { USB_DEVICE(0x04e8, 0xa100), .driver_info = FLAG_TYPE_SAMSUNG }, 666 { USB_DEVICE(0x17ef, 0x304b), .driver_info = FLAG_TYPE_LENOVO }, 667 { USB_DEVICE(0x04b4, 0x3610), .driver_info = FLAG_TYPE_GX3 }, 668 { } /* Terminating entry */ 669}; 670 671U_BOOT_USB_DEVICE(ax88179_eth, ax88179_eth_id_table); 672