1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2015 Realtek Semiconductor Corp. All rights reserved. 4 * 5 */ 6 7#include <common.h> 8#include <dm.h> 9#include <errno.h> 10#include <log.h> 11#include <malloc.h> 12#include <memalign.h> 13#include <net.h> 14#include <usb.h> 15#include <linux/delay.h> 16#include <linux/mii.h> 17#include <linux/bitops.h> 18#include "usb_ether.h" 19#include "r8152.h" 20 21struct r8152_version { 22 unsigned short tcr; 23 unsigned short version; 24 bool gmii; 25}; 26 27static const struct r8152_version r8152_versions[] = { 28 { 0x4c00, RTL_VER_01, 0 }, 29 { 0x4c10, RTL_VER_02, 0 }, 30 { 0x5c00, RTL_VER_03, 1 }, 31 { 0x5c10, RTL_VER_04, 1 }, 32 { 0x5c20, RTL_VER_05, 1 }, 33 { 0x5c30, RTL_VER_06, 1 }, 34 { 0x4800, RTL_VER_07, 0 }, 35 { 0x6000, RTL_VER_08, 1 }, 36 { 0x6010, RTL_VER_09, 1 }, 37}; 38 39static 40int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 41{ 42 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size); 43 int ret; 44 45 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), 46 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 47 value, index, tmp, size, 500); 48 memcpy(data, tmp, size); 49 return ret; 50} 51 52static 53int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 54{ 55 ALLOC_CACHE_ALIGN_BUFFER(void *, tmp, size); 56 57 memcpy(tmp, data, size); 58 return usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), 59 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 60 value, index, tmp, size, 500); 61} 62 63int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 64 void *data, u16 type) 65{ 66 u16 burst_size = 64; 67 int ret; 68 int txsize; 69 70 /* both size and index must be 4 bytes align */ 71 if ((size & 3) || !size || (index & 3) || !data) 72 return -EINVAL; 73 74 if (index + size > 0xffff) 75 return -EINVAL; 76 77 while (size) { 78 txsize = min(size, burst_size); 79 ret = get_registers(tp, index, type, txsize, data); 80 if (ret < 0) 81 break; 82 83 index += txsize; 84 data += txsize; 85 size -= txsize; 86 } 87 88 return ret; 89} 90 91int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 92 u16 size, void *data, u16 type) 93{ 94 int ret; 95 u16 byteen_start, byteen_end, byte_en_to_hw; 96 u16 burst_size = 512; 97 int txsize; 98 99 /* both size and index must be 4 bytes align */ 100 if ((size & 3) || !size || (index & 3) || !data) 101 return -EINVAL; 102 103 if (index + size > 0xffff) 104 return -EINVAL; 105 106 byteen_start = byteen & BYTE_EN_START_MASK; 107 byteen_end = byteen & BYTE_EN_END_MASK; 108 109 byte_en_to_hw = byteen_start | (byteen_start << 4); 110 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data); 111 if (ret < 0) 112 return ret; 113 114 index += 4; 115 data += 4; 116 size -= 4; 117 118 if (size) { 119 size -= 4; 120 121 while (size) { 122 txsize = min(size, burst_size); 123 124 ret = set_registers(tp, index, 125 type | BYTE_EN_DWORD, 126 txsize, data); 127 if (ret < 0) 128 return ret; 129 130 index += txsize; 131 data += txsize; 132 size -= txsize; 133 } 134 135 byte_en_to_hw = byteen_end | (byteen_end >> 4); 136 ret = set_registers(tp, index, type | byte_en_to_hw, 4, data); 137 if (ret < 0) 138 return ret; 139 } 140 141 return ret; 142} 143 144int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 145{ 146 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 147} 148 149int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 150{ 151 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 152} 153 154int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 155{ 156 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); 157} 158 159int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 160{ 161 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 162} 163 164u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 165{ 166 __le32 data; 167 168 generic_ocp_read(tp, index, sizeof(data), &data, type); 169 170 return __le32_to_cpu(data); 171} 172 173void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 174{ 175 __le32 tmp = __cpu_to_le32(data); 176 177 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 178} 179 180u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 181{ 182 u32 data; 183 __le32 tmp; 184 u8 shift = index & 2; 185 186 index &= ~3; 187 188 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 189 190 data = __le32_to_cpu(tmp); 191 data >>= (shift * 8); 192 data &= 0xffff; 193 194 return data; 195} 196 197void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 198{ 199 u32 mask = 0xffff; 200 __le32 tmp; 201 u16 byen = BYTE_EN_WORD; 202 u8 shift = index & 2; 203 204 data &= mask; 205 206 if (index & 2) { 207 byen <<= shift; 208 mask <<= (shift * 8); 209 data <<= (shift * 8); 210 index &= ~3; 211 } 212 213 tmp = __cpu_to_le32(data); 214 215 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 216} 217 218u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 219{ 220 u32 data; 221 __le32 tmp; 222 u8 shift = index & 3; 223 224 index &= ~3; 225 226 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 227 228 data = __le32_to_cpu(tmp); 229 data >>= (shift * 8); 230 data &= 0xff; 231 232 return data; 233} 234 235void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 236{ 237 u32 mask = 0xff; 238 __le32 tmp; 239 u16 byen = BYTE_EN_BYTE; 240 u8 shift = index & 3; 241 242 data &= mask; 243 244 if (index & 3) { 245 byen <<= shift; 246 mask <<= (shift * 8); 247 data <<= (shift * 8); 248 index &= ~3; 249 } 250 251 tmp = __cpu_to_le32(data); 252 253 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 254} 255 256u16 ocp_reg_read(struct r8152 *tp, u16 addr) 257{ 258 u16 ocp_base, ocp_index; 259 260 ocp_base = addr & 0xf000; 261 if (ocp_base != tp->ocp_base) { 262 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 263 tp->ocp_base = ocp_base; 264 } 265 266 ocp_index = (addr & 0x0fff) | 0xb000; 267 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 268} 269 270void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 271{ 272 u16 ocp_base, ocp_index; 273 274 ocp_base = addr & 0xf000; 275 if (ocp_base != tp->ocp_base) { 276 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 277 tp->ocp_base = ocp_base; 278 } 279 280 ocp_index = (addr & 0x0fff) | 0xb000; 281 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 282} 283 284static void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 285{ 286 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 287} 288 289static int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 290{ 291 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 292} 293 294void sram_write(struct r8152 *tp, u16 addr, u16 data) 295{ 296 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 297 ocp_reg_write(tp, OCP_SRAM_DATA, data); 298} 299 300static u16 sram_read(struct r8152 *tp, u16 addr) 301{ 302 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 303 return ocp_reg_read(tp, OCP_SRAM_DATA); 304} 305 306int r8152_wait_for_bit(struct r8152 *tp, bool ocp_reg, u16 type, u16 index, 307 const u32 mask, bool set, unsigned int timeout) 308{ 309 u32 val; 310 311 while (--timeout) { 312 if (ocp_reg) 313 val = ocp_reg_read(tp, index); 314 else 315 val = ocp_read_dword(tp, type, index); 316 317 if (!set) 318 val = ~val; 319 320 if ((val & mask) == mask) 321 return 0; 322 323 mdelay(1); 324 } 325 326 debug("%s: Timeout (index=%04x mask=%08x timeout=%d)\n", 327 __func__, index, mask, timeout); 328 329 return -ETIMEDOUT; 330} 331 332static void r8152b_reset_packet_filter(struct r8152 *tp) 333{ 334 u32 ocp_data; 335 336 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 337 ocp_data &= ~FMC_FCR_MCU_EN; 338 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 339 ocp_data |= FMC_FCR_MCU_EN; 340 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 341} 342 343static void rtl8152_wait_fifo_empty(struct r8152 *tp) 344{ 345 int ret; 346 347 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, 348 PLA_PHY_PWR_TXEMP, 1, R8152_WAIT_TIMEOUT); 349 if (ret) 350 debug("Timeout waiting for FIFO empty\n"); 351 352 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_TCR0, 353 TCR0_TX_EMPTY, 1, R8152_WAIT_TIMEOUT); 354 if (ret) 355 debug("Timeout waiting for TX empty\n"); 356} 357 358static void rtl8152_nic_reset(struct r8152 *tp) 359{ 360 int ret; 361 u32 ocp_data; 362 363 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, BIST_CTRL); 364 ocp_data |= BIST_CTRL_SW_RESET; 365 ocp_write_dword(tp, MCU_TYPE_PLA, BIST_CTRL, ocp_data); 366 367 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, BIST_CTRL, 368 BIST_CTRL_SW_RESET, 0, R8152_WAIT_TIMEOUT); 369 if (ret) 370 debug("Timeout waiting for NIC reset\n"); 371} 372 373static u8 rtl8152_get_speed(struct r8152 *tp) 374{ 375 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 376} 377 378static void rtl_set_eee_plus(struct r8152 *tp) 379{ 380 u32 ocp_data; 381 382 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 383 ocp_data &= ~EEEP_CR_EEEP_TX; 384 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 385} 386 387static void rxdy_gated_en(struct r8152 *tp, bool enable) 388{ 389 u32 ocp_data; 390 391 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 392 if (enable) 393 ocp_data |= RXDY_GATED_EN; 394 else 395 ocp_data &= ~RXDY_GATED_EN; 396 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 397} 398 399static void rtl8152_set_rx_mode(struct r8152 *tp) 400{ 401 u32 ocp_data; 402 __le32 tmp[2]; 403 404 tmp[0] = 0xffffffff; 405 tmp[1] = 0xffffffff; 406 407 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 408 409 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 410 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 411 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 412} 413 414static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 415{ 416 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 417 OWN_UPDATE | OWN_CLEAR); 418} 419 420static int rtl_enable(struct r8152 *tp) 421{ 422 u32 ocp_data; 423 424 r8152b_reset_packet_filter(tp); 425 426 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 427 ocp_data |= PLA_CR_RE | PLA_CR_TE; 428 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 429 430 switch (tp->version) { 431 case RTL_VER_08: 432 case RTL_VER_09: 433 r8153b_rx_agg_chg_indicate(tp); 434 break; 435 default: 436 break; 437 } 438 439 rxdy_gated_en(tp, false); 440 441 rtl8152_set_rx_mode(tp); 442 443 return 0; 444} 445 446static int rtl8152_enable(struct r8152 *tp) 447{ 448 rtl_set_eee_plus(tp); 449 450 return rtl_enable(tp); 451} 452 453static void r8153_set_rx_early_timeout(struct r8152 *tp) 454{ 455 u32 ocp_data = tp->coalesce / 8; 456 457 switch (tp->version) { 458 case RTL_VER_03: 459 case RTL_VER_04: 460 case RTL_VER_05: 461 case RTL_VER_06: 462 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 463 ocp_data); 464 break; 465 466 case RTL_VER_08: 467 case RTL_VER_09: 468 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 469 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 1264ns. 470 */ 471 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 472 RX_AUXILIARY_TIMER / 8); 473 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 474 ocp_data); 475 break; 476 477 default: 478 debug("** %s Invalid Device\n", __func__); 479 break; 480 } 481} 482 483static void r8153_set_rx_early_size(struct r8152 *tp) 484{ 485 u32 ocp_data = (RTL8152_AGG_BUF_SZ - RTL8153_RMS - 486 sizeof(struct rx_desc)); 487 488 switch (tp->version) { 489 case RTL_VER_03: 490 case RTL_VER_04: 491 case RTL_VER_05: 492 case RTL_VER_06: 493 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 494 ocp_data / 4); 495 break; 496 497 case RTL_VER_08: 498 case RTL_VER_09: 499 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 500 ocp_data / 8); 501 break; 502 503 default: 504 debug("** %s Invalid Device\n", __func__); 505 break; 506 } 507} 508 509static int rtl8153_enable(struct r8152 *tp) 510{ 511 rtl_set_eee_plus(tp); 512 r8153_set_rx_early_timeout(tp); 513 r8153_set_rx_early_size(tp); 514 515 return rtl_enable(tp); 516} 517 518static void rtl_disable(struct r8152 *tp) 519{ 520 u32 ocp_data; 521 522 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 523 ocp_data &= ~RCR_ACPT_ALL; 524 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 525 526 rxdy_gated_en(tp, true); 527 528 rtl8152_wait_fifo_empty(tp); 529 rtl8152_nic_reset(tp); 530} 531 532static void r8152_power_cut_en(struct r8152 *tp, bool enable) 533{ 534 u32 ocp_data; 535 536 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 537 if (enable) 538 ocp_data |= POWER_CUT; 539 else 540 ocp_data &= ~POWER_CUT; 541 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 542 543 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 544 ocp_data &= ~RESUME_INDICATE; 545 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 546} 547 548static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 549{ 550 u32 ocp_data; 551 552 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 553 if (enable) 554 ocp_data |= CPCR_RX_VLAN; 555 else 556 ocp_data &= ~CPCR_RX_VLAN; 557 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 558} 559 560static void r8153_u1u2en(struct r8152 *tp, bool enable) 561{ 562 u8 u1u2[8]; 563 564 if (enable) 565 memset(u1u2, 0xff, sizeof(u1u2)); 566 else 567 memset(u1u2, 0x00, sizeof(u1u2)); 568 569 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 570} 571 572static void r8153b_u1u2en(struct r8152 *tp, bool enable) 573{ 574 u16 ocp_data; 575 576 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 577 if (enable) 578 ocp_data |= LPM_U1U2_EN; 579 else 580 ocp_data &= ~LPM_U1U2_EN; 581 582 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 583} 584 585static void r8153_u2p3en(struct r8152 *tp, bool enable) 586{ 587 u32 ocp_data; 588 589 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 590 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) 591 ocp_data |= U2P3_ENABLE; 592 else 593 ocp_data &= ~U2P3_ENABLE; 594 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 595} 596 597static void r8153_power_cut_en(struct r8152 *tp, bool enable) 598{ 599 u32 ocp_data; 600 601 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 602 if (enable) 603 ocp_data |= PWR_EN | PHASE2_EN; 604 else 605 ocp_data &= ~(PWR_EN | PHASE2_EN); 606 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 607 608 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 609 ocp_data &= ~PCUT_STATUS; 610 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 611} 612 613static void rtl_reset_bmu(struct r8152 *tp) 614{ 615 u8 ocp_data; 616 617 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 618 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 619 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 620 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 621 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 622} 623 624static int r8152_read_mac(struct r8152 *tp, unsigned char *macaddr) 625{ 626 int ret; 627 unsigned char enetaddr[8] = {0}; 628 629 ret = pla_ocp_read(tp, PLA_IDR, 8, enetaddr); 630 if (ret < 0) 631 return ret; 632 633 memcpy(macaddr, enetaddr, ETH_ALEN); 634 return 0; 635} 636 637static void r8152b_disable_aldps(struct r8152 *tp) 638{ 639 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); 640 mdelay(20); 641} 642 643static void r8152b_enable_aldps(struct r8152 *tp) 644{ 645 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 646 LINKENA | DIS_SDSAVE); 647} 648 649static void rtl8152_disable(struct r8152 *tp) 650{ 651 r8152b_disable_aldps(tp); 652 rtl_disable(tp); 653 r8152b_enable_aldps(tp); 654} 655 656static void r8152b_hw_phy_cfg(struct r8152 *tp) 657{ 658 u16 data; 659 660 data = r8152_mdio_read(tp, MII_BMCR); 661 if (data & BMCR_PDOWN) { 662 data &= ~BMCR_PDOWN; 663 r8152_mdio_write(tp, MII_BMCR, data); 664 } 665 666 r8152b_firmware(tp); 667} 668 669static void rtl8152_reinit_ll(struct r8152 *tp) 670{ 671 u32 ocp_data; 672 int ret; 673 674 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, 675 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT); 676 if (ret) 677 debug("Timeout waiting for link list ready\n"); 678 679 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 680 ocp_data |= RE_INIT_LL; 681 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 682 683 ret = r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_PHY_PWR, 684 PLA_PHY_PWR_LLR, 1, R8152_WAIT_TIMEOUT); 685 if (ret) 686 debug("Timeout waiting for link list ready\n"); 687} 688 689static void r8152b_exit_oob(struct r8152 *tp) 690{ 691 u32 ocp_data; 692 693 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 694 ocp_data &= ~RCR_ACPT_ALL; 695 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 696 697 rxdy_gated_en(tp, true); 698 r8152b_hw_phy_cfg(tp); 699 700 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 701 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 702 703 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 704 ocp_data &= ~NOW_IS_OOB; 705 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 706 707 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 708 ocp_data &= ~MCU_BORW_EN; 709 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 710 711 rtl8152_reinit_ll(tp); 712 rtl8152_nic_reset(tp); 713 714 /* rx share fifo credit full threshold */ 715 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 716 717 if (tp->udev->speed == USB_SPEED_FULL || 718 tp->udev->speed == USB_SPEED_LOW) { 719 /* rx share fifo credit near full threshold */ 720 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 721 RXFIFO_THR2_FULL); 722 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 723 RXFIFO_THR3_FULL); 724 } else { 725 /* rx share fifo credit near full threshold */ 726 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 727 RXFIFO_THR2_HIGH); 728 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 729 RXFIFO_THR3_HIGH); 730 } 731 732 /* TX share fifo free credit full threshold */ 733 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); 734 735 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 736 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 737 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 738 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 739 740 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 741 742 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 743 ocp_data |= TCR0_AUTO_FIFO; 744 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 745} 746 747static void r8152b_enter_oob(struct r8152 *tp) 748{ 749 u32 ocp_data; 750 751 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 752 ocp_data &= ~NOW_IS_OOB; 753 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 754 755 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 756 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 757 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 758 759 rtl_disable(tp); 760 761 rtl8152_reinit_ll(tp); 762 763 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 764 765 rtl_rx_vlan_en(tp, false); 766 767 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 768 ocp_data |= ALDPS_PROXY_MODE; 769 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 770 771 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 772 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 773 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 774 775 rxdy_gated_en(tp, false); 776 777 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 778 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 779 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 780} 781 782static void r8153_hw_phy_cfg(struct r8152 *tp) 783{ 784 u32 ocp_data; 785 u16 data; 786 787 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 788 tp->version == RTL_VER_05) 789 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 790 791 data = r8152_mdio_read(tp, MII_BMCR); 792 if (data & BMCR_PDOWN) { 793 data &= ~BMCR_PDOWN; 794 r8152_mdio_write(tp, MII_BMCR, data); 795 } 796 797 r8153_firmware(tp); 798 799 if (tp->version == RTL_VER_03) { 800 data = ocp_reg_read(tp, OCP_EEE_CFG); 801 data &= ~CTAP_SHORT_EN; 802 ocp_reg_write(tp, OCP_EEE_CFG, data); 803 } 804 805 data = ocp_reg_read(tp, OCP_POWER_CFG); 806 data |= EEE_CLKDIV_EN; 807 ocp_reg_write(tp, OCP_POWER_CFG, data); 808 809 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 810 data |= EN_10M_BGOFF; 811 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 812 data = ocp_reg_read(tp, OCP_POWER_CFG); 813 data |= EN_10M_PLLOFF; 814 ocp_reg_write(tp, OCP_POWER_CFG, data); 815 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 816 817 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 818 ocp_data |= PFM_PWM_SWITCH; 819 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 820 821 /* Enable LPF corner auto tune */ 822 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 823 824 /* Adjust 10M Amplitude */ 825 sram_write(tp, SRAM_10M_AMP1, 0x00af); 826 sram_write(tp, SRAM_10M_AMP2, 0x0208); 827} 828 829static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 830{ 831 u32 ocp_data; 832 833 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 834 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 835 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 836 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 837 838 return ocp_data; 839} 840 841static void r8153b_hw_phy_cfg(struct r8152 *tp) 842{ 843 u32 ocp_data; 844 u16 data; 845 846 data = r8152_mdio_read(tp, MII_BMCR); 847 if (data & BMCR_PDOWN) { 848 data &= ~BMCR_PDOWN; 849 r8152_mdio_write(tp, MII_BMCR, data); 850 } 851 852 /* U1/U2/L1 idle timer. 500 us */ 853 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 854 855 r8153b_firmware(tp); 856 857 data = sram_read(tp, SRAM_GREEN_CFG); 858 data |= R_TUNE_EN; 859 sram_write(tp, SRAM_GREEN_CFG, data); 860 data = ocp_reg_read(tp, OCP_NCTL_CFG); 861 data |= PGA_RETURN_EN; 862 ocp_reg_write(tp, OCP_NCTL_CFG, data); 863 864 /* ADC Bias Calibration: 865 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 866 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 867 * ADC ioffset. 868 */ 869 ocp_data = r8152_efuse_read(tp, 0x7d); 870 ocp_data = ((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7); 871 if (ocp_data != 0xffff) 872 ocp_reg_write(tp, OCP_ADC_IOFFSET, ocp_data); 873 874 /* ups mode tx-link-pulse timing adjustment: 875 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 876 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 877 */ 878 ocp_data = ocp_reg_read(tp, 0xc426); 879 ocp_data &= 0x3fff; 880 if (ocp_data) { 881 u32 swr_cnt_1ms_ini; 882 883 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 884 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 885 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 886 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 887 } 888 889 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 890 ocp_data |= PFM_PWM_SWITCH; 891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 892} 893 894static void r8153_first_init(struct r8152 *tp) 895{ 896 u32 ocp_data; 897 898 rxdy_gated_en(tp, true); 899 900 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 901 ocp_data &= ~RCR_ACPT_ALL; 902 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 903 904 r8153_hw_phy_cfg(tp); 905 906 rtl8152_nic_reset(tp); 907 rtl_reset_bmu(tp); 908 909 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 910 ocp_data &= ~NOW_IS_OOB; 911 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 912 913 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 914 ocp_data &= ~MCU_BORW_EN; 915 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 916 917 rtl8152_reinit_ll(tp); 918 919 rtl_rx_vlan_en(tp, false); 920 921 ocp_data = RTL8153_RMS; 922 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 923 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 924 925 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 926 ocp_data |= TCR0_AUTO_FIFO; 927 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 928 929 rtl8152_nic_reset(tp); 930 931 /* rx share fifo credit full threshold */ 932 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 933 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 934 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 935 /* TX share fifo free credit full threshold */ 936 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 937 938 /* rx aggregation */ 939 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 940 941 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 942 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 943} 944 945static void r8153_enter_oob(struct r8152 *tp) 946{ 947 u32 ocp_data; 948 949 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 950 ocp_data &= ~NOW_IS_OOB; 951 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 952 953 rtl_disable(tp); 954 rtl_reset_bmu(tp); 955 956 rtl8152_reinit_ll(tp); 957 958 ocp_data = RTL8153_RMS; 959 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); 960 961 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 962 ocp_data &= ~TEREDO_WAKE_MASK; 963 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 964 965 rtl_rx_vlan_en(tp, false); 966 967 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 968 ocp_data |= ALDPS_PROXY_MODE; 969 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 970 971 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 972 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 973 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 974 975 rxdy_gated_en(tp, false); 976 977 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 978 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 979 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 980} 981 982static void r8153_disable_aldps(struct r8152 *tp) 983{ 984 u16 data; 985 986 data = ocp_reg_read(tp, OCP_POWER_CFG); 987 data &= ~EN_ALDPS; 988 ocp_reg_write(tp, OCP_POWER_CFG, data); 989 mdelay(20); 990} 991 992static void rtl8153_disable(struct r8152 *tp) 993{ 994 r8153_disable_aldps(tp); 995 rtl_disable(tp); 996 rtl_reset_bmu(tp); 997} 998 999static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) 1000{ 1001 u16 bmcr, anar, gbcr; 1002 1003 anar = r8152_mdio_read(tp, MII_ADVERTISE); 1004 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 1005 ADVERTISE_100HALF | ADVERTISE_100FULL); 1006 if (tp->supports_gmii) { 1007 gbcr = r8152_mdio_read(tp, MII_CTRL1000); 1008 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); 1009 } else { 1010 gbcr = 0; 1011 } 1012 1013 if (autoneg == AUTONEG_DISABLE) { 1014 if (speed == SPEED_10) { 1015 bmcr = 0; 1016 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1017 } else if (speed == SPEED_100) { 1018 bmcr = BMCR_SPEED100; 1019 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 1020 } else if (speed == SPEED_1000 && tp->supports_gmii) { 1021 bmcr = BMCR_SPEED1000; 1022 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 1023 } else { 1024 return -EINVAL; 1025 } 1026 1027 if (duplex == DUPLEX_FULL) 1028 bmcr |= BMCR_FULLDPLX; 1029 } else { 1030 if (speed == SPEED_10) { 1031 if (duplex == DUPLEX_FULL) 1032 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1033 else 1034 anar |= ADVERTISE_10HALF; 1035 } else if (speed == SPEED_100) { 1036 if (duplex == DUPLEX_FULL) { 1037 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1038 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 1039 } else { 1040 anar |= ADVERTISE_10HALF; 1041 anar |= ADVERTISE_100HALF; 1042 } 1043 } else if (speed == SPEED_1000 && tp->supports_gmii) { 1044 if (duplex == DUPLEX_FULL) { 1045 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; 1046 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; 1047 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; 1048 } else { 1049 anar |= ADVERTISE_10HALF; 1050 anar |= ADVERTISE_100HALF; 1051 gbcr |= ADVERTISE_1000HALF; 1052 } 1053 } else { 1054 return -EINVAL; 1055 } 1056 1057 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; 1058 } 1059 1060 if (tp->supports_gmii) 1061 r8152_mdio_write(tp, MII_CTRL1000, gbcr); 1062 1063 r8152_mdio_write(tp, MII_ADVERTISE, anar); 1064 r8152_mdio_write(tp, MII_BMCR, bmcr); 1065 1066 return 0; 1067} 1068 1069static void rtl8152_up(struct r8152 *tp) 1070{ 1071 r8152b_disable_aldps(tp); 1072 r8152b_exit_oob(tp); 1073 r8152b_enable_aldps(tp); 1074} 1075 1076static void rtl8152_down(struct r8152 *tp) 1077{ 1078 r8152_power_cut_en(tp, false); 1079 r8152b_disable_aldps(tp); 1080 r8152b_enter_oob(tp); 1081 r8152b_enable_aldps(tp); 1082} 1083 1084static void rtl8153_up(struct r8152 *tp) 1085{ 1086 r8153_u1u2en(tp, false); 1087 r8153_disable_aldps(tp); 1088 r8153_first_init(tp); 1089 r8153_u2p3en(tp, false); 1090} 1091 1092static void rtl8153_down(struct r8152 *tp) 1093{ 1094 r8153_u1u2en(tp, false); 1095 r8153_u2p3en(tp, false); 1096 r8153_power_cut_en(tp, false); 1097 r8153_disable_aldps(tp); 1098 r8153_enter_oob(tp); 1099} 1100 1101static void rtl8153b_up(struct r8152 *tp) 1102{ 1103 r8153_first_init(tp); 1104} 1105 1106static void rtl8153b_down(struct r8152 *tp) 1107{ 1108 r8153_enter_oob(tp); 1109} 1110 1111static void r8152b_get_version(struct r8152 *tp) 1112{ 1113 u32 ocp_data; 1114 u16 tcr; 1115 int i; 1116 1117 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 1118 tcr = (u16)(ocp_data & VERSION_MASK); 1119 1120 for (i = 0; i < ARRAY_SIZE(r8152_versions); i++) { 1121 if (tcr == r8152_versions[i].tcr) { 1122 /* Found a supported version */ 1123 tp->version = r8152_versions[i].version; 1124 tp->supports_gmii = r8152_versions[i].gmii; 1125 break; 1126 } 1127 } 1128 1129 if (tp->version == RTL_VER_UNKNOWN) 1130 debug("r8152 Unknown tcr version 0x%04x\n", tcr); 1131} 1132 1133static void r8152b_enable_fc(struct r8152 *tp) 1134{ 1135 u16 anar; 1136 anar = r8152_mdio_read(tp, MII_ADVERTISE); 1137 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 1138 r8152_mdio_write(tp, MII_ADVERTISE, anar); 1139} 1140 1141static void rtl_tally_reset(struct r8152 *tp) 1142{ 1143 u32 ocp_data; 1144 1145 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 1146 ocp_data |= TALLY_RESET; 1147 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 1148} 1149 1150static void r8152b_init(struct r8152 *tp) 1151{ 1152 u32 ocp_data; 1153 1154 r8152b_disable_aldps(tp); 1155 1156 if (tp->version == RTL_VER_01) { 1157 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 1158 ocp_data &= ~LED_MODE_MASK; 1159 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 1160 } 1161 1162 r8152_power_cut_en(tp, false); 1163 1164 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 1165 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 1166 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 1167 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 1168 ocp_data &= ~MCU_CLK_RATIO_MASK; 1169 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 1170 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 1171 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 1172 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 1173 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 1174 1175 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_TIMER); 1176 ocp_data |= BIT(15); 1177 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data); 1178 ocp_write_word(tp, MCU_TYPE_USB, 0xcbfc, 0x03e8); 1179 ocp_data &= ~BIT(15); 1180 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_TIMER, ocp_data); 1181 1182 r8152b_enable_fc(tp); 1183 rtl_tally_reset(tp); 1184 1185 /* enable rx aggregation */ 1186 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 1187 1188 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 1189 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 1190} 1191 1192static void r8153_init(struct r8152 *tp) 1193{ 1194 int i; 1195 u32 ocp_data; 1196 1197 r8153_disable_aldps(tp); 1198 r8153_u1u2en(tp, false); 1199 1200 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL, 1201 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT); 1202 1203 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) { 1204 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 1205 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 1206 break; 1207 1208 mdelay(1); 1209 } 1210 1211 r8153_u2p3en(tp, false); 1212 1213 if (tp->version == RTL_VER_04) { 1214 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 1215 ocp_data &= ~pwd_dn_scale_mask; 1216 ocp_data |= pwd_dn_scale(96); 1217 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 1218 1219 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 1220 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 1221 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 1222 } else if (tp->version == RTL_VER_05) { 1223 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 1224 ocp_data &= ~ECM_ALDPS; 1225 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 1226 1227 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 1228 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 1229 ocp_data &= ~DYNAMIC_BURST; 1230 else 1231 ocp_data |= DYNAMIC_BURST; 1232 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 1233 } else if (tp->version == RTL_VER_06) { 1234 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 1235 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 1236 ocp_data &= ~DYNAMIC_BURST; 1237 else 1238 ocp_data |= DYNAMIC_BURST; 1239 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 1240 } 1241 1242 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 1243 ocp_data |= EP4_FULL_FC; 1244 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 1245 1246 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 1247 ocp_data &= ~TIMER11_EN; 1248 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 1249 1250 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 1251 ocp_data &= ~LED_MODE_MASK; 1252 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 1253 1254 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 1255 if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER) 1256 ocp_data |= LPM_TIMER_500MS; 1257 else 1258 ocp_data |= LPM_TIMER_500US; 1259 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 1260 1261 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 1262 ocp_data &= ~SEN_VAL_MASK; 1263 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 1264 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 1265 1266 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 1267 1268 r8153_power_cut_en(tp, false); 1269 1270 r8152b_enable_fc(tp); 1271 rtl_tally_reset(tp); 1272} 1273 1274static void r8153b_init(struct r8152 *tp) 1275{ 1276 u32 ocp_data; 1277 int i; 1278 1279 r8153_disable_aldps(tp); 1280 r8153b_u1u2en(tp, false); 1281 1282 r8152_wait_for_bit(tp, 0, MCU_TYPE_PLA, PLA_BOOT_CTRL, 1283 AUTOLOAD_DONE, 1, R8152_WAIT_TIMEOUT); 1284 1285 for (i = 0; i < R8152_WAIT_TIMEOUT; i++) { 1286 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; 1287 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) 1288 break; 1289 1290 mdelay(1); 1291 } 1292 1293 r8153_u2p3en(tp, false); 1294 1295 /* MSC timer = 0xfff * 8ms = 32760 ms */ 1296 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 1297 1298 r8153_power_cut_en(tp, false); 1299 1300 /* MAC clock speed down */ 1301 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 1302 ocp_data |= MAC_CLK_SPDWN_EN; 1303 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 1304 1305 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 1306 ocp_data &= ~PLA_MCU_SPDWN_EN; 1307 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 1308 1309 if (tp->version == RTL_VER_09) { 1310 /* Disable Test IO for 32QFN */ 1311 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { 1312 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 1313 ocp_data |= TEST_IO_OFF; 1314 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 1315 } 1316 } 1317 1318 /* rx aggregation */ 1319 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 1320 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 1321 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 1322 1323 rtl_tally_reset(tp); 1324 r8153b_hw_phy_cfg(tp); 1325 r8152b_enable_fc(tp); 1326} 1327 1328static void rtl8152_unload(struct r8152 *tp) 1329{ 1330 if (tp->version != RTL_VER_01) 1331 r8152_power_cut_en(tp, true); 1332} 1333 1334static void rtl8153_unload(struct r8152 *tp) 1335{ 1336 r8153_power_cut_en(tp, false); 1337} 1338 1339static int rtl_ops_init(struct r8152 *tp) 1340{ 1341 struct rtl_ops *ops = &tp->rtl_ops; 1342 int ret = 0; 1343 1344 switch (tp->version) { 1345 case RTL_VER_01: 1346 case RTL_VER_02: 1347 case RTL_VER_07: 1348 ops->init = r8152b_init; 1349 ops->enable = rtl8152_enable; 1350 ops->disable = rtl8152_disable; 1351 ops->up = rtl8152_up; 1352 ops->down = rtl8152_down; 1353 ops->unload = rtl8152_unload; 1354 break; 1355 1356 case RTL_VER_03: 1357 case RTL_VER_04: 1358 case RTL_VER_05: 1359 case RTL_VER_06: 1360 ops->init = r8153_init; 1361 ops->enable = rtl8153_enable; 1362 ops->disable = rtl8153_disable; 1363 ops->up = rtl8153_up; 1364 ops->down = rtl8153_down; 1365 ops->unload = rtl8153_unload; 1366 break; 1367 1368 case RTL_VER_08: 1369 case RTL_VER_09: 1370 ops->init = r8153b_init; 1371 ops->enable = rtl8153_enable; 1372 ops->disable = rtl8153_disable; 1373 ops->up = rtl8153b_up; 1374 ops->down = rtl8153b_down; 1375 break; 1376 1377 default: 1378 ret = -ENODEV; 1379 printf("r8152 Unknown Device\n"); 1380 break; 1381 } 1382 1383 return ret; 1384} 1385 1386static int r8152_init_common(struct r8152 *tp) 1387{ 1388 u8 speed; 1389 int timeout = 0; 1390 int link_detected; 1391 1392 debug("** %s()\n", __func__); 1393 1394 do { 1395 speed = rtl8152_get_speed(tp); 1396 1397 link_detected = speed & LINK_STATUS; 1398 if (!link_detected) { 1399 if (timeout == 0) 1400 printf("Waiting for Ethernet connection... "); 1401 mdelay(TIMEOUT_RESOLUTION); 1402 timeout += TIMEOUT_RESOLUTION; 1403 } 1404 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT); 1405 if (link_detected) { 1406 tp->rtl_ops.enable(tp); 1407 1408 if (timeout != 0) 1409 printf("done.\n"); 1410 } else { 1411 printf("unable to connect.\n"); 1412 } 1413 1414 return 0; 1415} 1416 1417static int r8152_send_common(struct ueth_data *ueth, void *packet, int length) 1418{ 1419 struct usb_device *udev = ueth->pusb_dev; 1420 u32 opts1, opts2 = 0; 1421 int err; 1422 int actual_len; 1423 ALLOC_CACHE_ALIGN_BUFFER(uint8_t, msg, 1424 PKTSIZE + sizeof(struct tx_desc)); 1425 struct tx_desc *tx_desc = (struct tx_desc *)msg; 1426 1427 debug("** %s(), len %d\n", __func__, length); 1428 1429 opts1 = length | TX_FS | TX_LS; 1430 1431 tx_desc->opts2 = cpu_to_le32(opts2); 1432 tx_desc->opts1 = cpu_to_le32(opts1); 1433 1434 memcpy(msg + sizeof(struct tx_desc), (void *)packet, length); 1435 1436 err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out), 1437 (void *)msg, length + sizeof(struct tx_desc), 1438 &actual_len, USB_BULK_SEND_TIMEOUT); 1439 debug("Tx: len = %zu, actual = %u, err = %d\n", 1440 length + sizeof(struct tx_desc), actual_len, err); 1441 1442 return err; 1443} 1444 1445static int r8152_eth_start(struct udevice *dev) 1446{ 1447 struct r8152 *tp = dev_get_priv(dev); 1448 1449 debug("** %s (%d)\n", __func__, __LINE__); 1450 1451 return r8152_init_common(tp); 1452} 1453 1454void r8152_eth_stop(struct udevice *dev) 1455{ 1456 struct r8152 *tp = dev_get_priv(dev); 1457 1458 debug("** %s (%d)\n", __func__, __LINE__); 1459 1460 tp->rtl_ops.disable(tp); 1461} 1462 1463int r8152_eth_send(struct udevice *dev, void *packet, int length) 1464{ 1465 struct r8152 *tp = dev_get_priv(dev); 1466 1467 return r8152_send_common(&tp->ueth, packet, length); 1468} 1469 1470int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp) 1471{ 1472 struct r8152 *tp = dev_get_priv(dev); 1473 struct ueth_data *ueth = &tp->ueth; 1474 uint8_t *ptr; 1475 int ret, len; 1476 struct rx_desc *rx_desc; 1477 u16 packet_len; 1478 1479 len = usb_ether_get_rx_bytes(ueth, &ptr); 1480 debug("%s: first try, len=%d\n", __func__, len); 1481 if (!len) { 1482 if (!(flags & ETH_RECV_CHECK_DEVICE)) 1483 return -EAGAIN; 1484 ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ); 1485 if (ret) 1486 return ret; 1487 1488 len = usb_ether_get_rx_bytes(ueth, &ptr); 1489 debug("%s: second try, len=%d\n", __func__, len); 1490 } 1491 1492 rx_desc = (struct rx_desc *)ptr; 1493 packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 1494 packet_len -= CRC_SIZE; 1495 1496 if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) { 1497 debug("Rx: too large packet: %d\n", packet_len); 1498 goto err; 1499 } 1500 1501 *packetp = ptr + sizeof(struct rx_desc); 1502 return packet_len; 1503 1504err: 1505 usb_ether_advance_rxbuf(ueth, -1); 1506 return -ENOSPC; 1507} 1508 1509static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len) 1510{ 1511 struct r8152 *tp = dev_get_priv(dev); 1512 1513 packet_len += sizeof(struct rx_desc) + CRC_SIZE; 1514 packet_len = ALIGN(packet_len, 8); 1515 usb_ether_advance_rxbuf(&tp->ueth, packet_len); 1516 1517 return 0; 1518} 1519 1520static int r8152_write_hwaddr(struct udevice *dev) 1521{ 1522 struct eth_pdata *pdata = dev_get_plat(dev); 1523 struct r8152 *tp = dev_get_priv(dev); 1524 1525 unsigned char enetaddr[8] = { 0 }; 1526 1527 debug("** %s (%d)\n", __func__, __LINE__); 1528 memcpy(enetaddr, pdata->enetaddr, ETH_ALEN); 1529 1530 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1531 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); 1532 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1533 1534 debug("MAC %pM\n", pdata->enetaddr); 1535 return 0; 1536} 1537 1538int r8152_read_rom_hwaddr(struct udevice *dev) 1539{ 1540 struct eth_pdata *pdata = dev_get_plat(dev); 1541 struct r8152 *tp = dev_get_priv(dev); 1542 1543 debug("** %s (%d)\n", __func__, __LINE__); 1544 r8152_read_mac(tp, pdata->enetaddr); 1545 return 0; 1546} 1547 1548static int r8152_eth_probe(struct udevice *dev) 1549{ 1550 struct usb_device *udev = dev_get_parent_priv(dev); 1551 struct eth_pdata *pdata = dev_get_plat(dev); 1552 struct r8152 *tp = dev_get_priv(dev); 1553 struct ueth_data *ueth = &tp->ueth; 1554 int ret; 1555 1556 tp->udev = udev; 1557 r8152_read_mac(tp, pdata->enetaddr); 1558 1559 r8152b_get_version(tp); 1560 1561 ret = rtl_ops_init(tp); 1562 if (ret) 1563 return ret; 1564 1565 tp->rtl_ops.init(tp); 1566 tp->rtl_ops.up(tp); 1567 1568 rtl8152_set_speed(tp, AUTONEG_ENABLE, 1569 tp->supports_gmii ? SPEED_1000 : SPEED_100, 1570 DUPLEX_FULL); 1571 1572 return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ); 1573} 1574 1575static const struct eth_ops r8152_eth_ops = { 1576 .start = r8152_eth_start, 1577 .send = r8152_eth_send, 1578 .recv = r8152_eth_recv, 1579 .free_pkt = r8152_free_pkt, 1580 .stop = r8152_eth_stop, 1581 .write_hwaddr = r8152_write_hwaddr, 1582 .read_rom_hwaddr = r8152_read_rom_hwaddr, 1583}; 1584 1585U_BOOT_DRIVER(r8152_eth) = { 1586 .name = "r8152_eth", 1587 .id = UCLASS_ETH, 1588 .probe = r8152_eth_probe, 1589 .ops = &r8152_eth_ops, 1590 .priv_auto = sizeof(struct r8152), 1591 .plat_auto = sizeof(struct eth_pdata), 1592}; 1593 1594static const struct usb_device_id r8152_eth_id_table[] = { 1595 /* Realtek */ 1596 { USB_DEVICE(0x0bda, 0x8050) }, 1597 { USB_DEVICE(0x0bda, 0x8152) }, 1598 { USB_DEVICE(0x0bda, 0x8153) }, 1599 1600 /* Samsung */ 1601 { USB_DEVICE(0x04e8, 0xa101) }, 1602 1603 /* Lenovo */ 1604 { USB_DEVICE(0x17ef, 0x304f) }, 1605 { USB_DEVICE(0x17ef, 0x3052) }, 1606 { USB_DEVICE(0x17ef, 0x3054) }, 1607 { USB_DEVICE(0x17ef, 0x3057) }, 1608 { USB_DEVICE(0x17ef, 0x7205) }, 1609 { USB_DEVICE(0x17ef, 0x720a) }, 1610 { USB_DEVICE(0x17ef, 0x720b) }, 1611 { USB_DEVICE(0x17ef, 0x720c) }, 1612 1613 /* TP-LINK */ 1614 { USB_DEVICE(0x2357, 0x0601) }, 1615 { USB_DEVICE(0x2357, 0x0602) }, 1616 1617 /* Nvidia */ 1618 { USB_DEVICE(0x0955, 0x09ff) }, 1619 1620 { } /* Terminating entry */ 1621}; 1622 1623U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table); 1624