1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8#include <init.h>
9#include <net.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/imx-regs.h>
12#include <asm/arch/iomux.h>
13#include <env.h>
14#include <malloc.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/global_data.h>
17#include <linux/delay.h>
18#include <linux/errno.h>
19#include <asm/gpio.h>
20#include <asm/mach-imx/iomux-v3.h>
21#include <asm/mach-imx/sata.h>
22#include <asm/arch/crm_regs.h>
23#include <asm/io.h>
24#include <asm/arch/sys_proto.h>
25#include <micrel.h>
26#include <miiphy.h>
27#include <netdev.h>
28
29DECLARE_GLOBAL_DATA_PTR;
30
31#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
32	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
33	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
34
35#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
36	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
37
38#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
39	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
40	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
41
42#define WDT_EN		IMX_GPIO_NR(5, 4)
43#define WDT_TRG		IMX_GPIO_NR(3, 19)
44
45int dram_init(void)
46{
47	gd->ram_size = imx_ddr_size();
48
49	return 0;
50}
51
52static iomux_v3_cfg_t const uart2_pads[] = {
53	IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
54	IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
55};
56
57static iomux_v3_cfg_t const wdog_pads[] = {
58	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
59	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
60};
61
62int mx6_rgmii_rework(struct phy_device *phydev)
63{
64	/*
65	 * Bug: Apparently uDoo does not works with Gigabit switches...
66	 * Limiting speed to 10/100Mbps, and setting master mode, seems to
67	 * be the only way to have a successfull PHY auto negotiation.
68	 * How to fix: Understand why Linux kernel do not have this issue.
69	 */
70	phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
71
72	/* control data pad skew - devaddr = 0x02, register = 0x04 */
73	ksz9031_phy_extended_write(phydev, 0x02,
74				   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
75				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
76	/* rx data pad skew - devaddr = 0x02, register = 0x05 */
77	ksz9031_phy_extended_write(phydev, 0x02,
78				   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
79				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
80	/* tx data pad skew - devaddr = 0x02, register = 0x05 */
81	ksz9031_phy_extended_write(phydev, 0x02,
82				   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
83				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
84	/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
85	ksz9031_phy_extended_write(phydev, 0x02,
86				   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
87				   MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
88	return 0;
89}
90
91static void setup_iomux_enet(void)
92{
93	gpio_request(IMX_GPIO_NR(2, 31), "eth_power");
94	gpio_request(IMX_GPIO_NR(3, 23), "eth_phy_reset");
95	gpio_request(IMX_GPIO_NR(6, 24), "strap1");
96	gpio_request(IMX_GPIO_NR(6, 25), "strap2");
97	gpio_request(IMX_GPIO_NR(6, 27), "strap3");
98	gpio_request(IMX_GPIO_NR(6, 28), "strap4");
99	gpio_request(IMX_GPIO_NR(6, 29), "strap5");
100
101	gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
102
103	gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
104
105	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
106	gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
107	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
108	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
109	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
110	udelay(1000);
111
112	gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
113
114	/* Need 100ms delay to exit from reset. */
115	udelay(1000 * 100);
116
117	gpio_free(IMX_GPIO_NR(6, 24));
118	gpio_free(IMX_GPIO_NR(6, 25));
119	gpio_free(IMX_GPIO_NR(6, 27));
120	gpio_free(IMX_GPIO_NR(6, 28));
121	gpio_free(IMX_GPIO_NR(6, 29));
122}
123
124static void setup_iomux_uart(void)
125{
126	SETUP_IOMUX_PADS(uart2_pads);
127}
128
129static void setup_iomux_wdog(void)
130{
131	SETUP_IOMUX_PADS(wdog_pads);
132	gpio_direction_output(WDT_TRG, 0);
133	gpio_direction_output(WDT_EN, 1);
134	gpio_direction_input(WDT_TRG);
135}
136
137int board_early_init_f(void)
138{
139	setup_iomux_wdog();
140	setup_iomux_uart();
141
142	return 0;
143}
144
145int board_phy_config(struct phy_device *phydev)
146{
147	mx6_rgmii_rework(phydev);
148	if (phydev->drv->config)
149		phydev->drv->config(phydev);
150
151	return 0;
152}
153
154int board_init(void)
155{
156	/* address of boot parameters */
157	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
158
159	return 0;
160}
161
162int board_late_init(void)
163{
164#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
165	if (is_cpu_type(MXC_CPU_MX6Q))
166		env_set("board_rev", "MX6Q");
167	else
168		env_set("board_rev", "MX6DL");
169#endif
170	setup_iomux_enet();
171
172	return 0;
173}
174
175int checkboard(void)
176{
177	if (is_cpu_type(MXC_CPU_MX6Q))
178		puts("Board: Udoo Quad\n");
179	else
180		puts("Board: Udoo DualLite\n");
181
182	return 0;
183}
184