| /u-boot/drivers/ddr/imx/phy/ |
| H A D | ddrphy_utils.c | 111 dram_pll_init(MHZ(1000));
117 dram_pll_init(MHZ(933));
121 dram_pll_init(MHZ(900));
125 dram_pll_init(MHZ(800));
129 dram_pll_init(MHZ(750));
133 dram_pll_init(MHZ(700));
137 dram_pll_init(MHZ(600));
141 dram_pll_init(MHZ(466));
145 dram_pll_init(MHZ(400));
149 dram_pll_init(MHZ(26
[all...] |
| /u-boot/drivers/video/exynos/ |
| H A D | exynos_mipi_dsi_common.c | 18 #define MHZ (1000 * 1000) macro
19 #define FIN_HZ (24 * MHZ)
21 #define DFIN_PLL_MIN_HZ (6 * MHZ)
22 #define DFIN_PLL_MAX_HZ (12 * MHZ)
24 #define DFVCO_MIN_HZ (500 * MHZ)
25 #define DFVCO_MAX_HZ (1000 * MHZ)
110 delay_val = MHZ / dsim->dsim_config->esc_clk;
289 if (dfin_pll < 7 * MHZ)
291 else if (dfin_pll < 8 * MHZ)
293 else if (dfin_pll < 9 * MHZ)
[all...] |
| /u-boot/drivers/clk/rockchip/ |
| H A D | clk_pll.c | 35 #define MHZ 1000000 macro
45 #define MIN_FOUTVCO_FREQ (800 * MHZ)
46 #define MAX_FOUTVCO_FREQ (2000 * MHZ)
47 #define RK3588_VCO_MIN_HZ (2250UL * MHZ)
48 #define RK3588_VCO_MAX_HZ (4500UL * MHZ)
49 #define RK3588_FOUT_MIN_HZ (37UL * MHZ)
50 #define RK3588_FOUT_MAX_HZ (4500UL * MHZ)
129 if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MH
[all...] |
| /u-boot/arch/arm/include/asm/arch-imx8ulp/ |
| H A D | clock.h | 12 #define MHZ(X) ((X) * 1000000UL) macro
|
| /u-boot/arch/arm/mach-imx/imx8m/ |
| H A D | clock_imx8mm.c | 140 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
142 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
144 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
234 case MHZ(600):
239 case MHZ(750):
244 case MHZ(800):
249 case MHZ(1000):
254 case MHZ(1200):
259 case MHZ(1400):
264 case MHZ(150
[all...] |
| H A D | clock_imx8mq.c | 571 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
573 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
575 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
627 case MHZ(800):
639 case MHZ(600):
651 case MHZ(400):
663 case MHZ(167):
|
| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mt7623.c | 21 #define MT7623_PLL_FMAX (2000UL * MHZ)
85 FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
86 FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
87 FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
88 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
89 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
90 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
91 FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
92 FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
93 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
[all...] |
| H A D | clk-mtk.h | 12 #define MHZ (1000 * 1000) macro
|
| H A D | clk-mt8365.c | 17 #define MT8365_PLL_FMAX (3800UL * MHZ)
18 #define MT8365_PLL_FMIN (1500UL * MHZ)
481 .xtal_rate = 26 * MHZ,
482 .xtal2_rate = 26 * MHZ,
|
| H A D | clk-mt7622.c | 21 #define MT7622_PLL_FMAX (2500UL * MHZ)
555 .xtal_rate = 25 * MHZ,
556 .xtal2_rate = 25 * MHZ,
|
| H A D | clk-mt7629.c | 21 #define MT7629_PLL_FMAX (2500UL * MHZ)
568 .xtal_rate = 40 * MHZ,
569 .xtal2_rate = 20 * MHZ,
|
| H A D | clk-mt8516.c | 17 #define MT8516_PLL_FMAX (1502UL * MHZ)
735 .xtal_rate = 26 * MHZ,
736 .xtal2_rate = 26 * MHZ,
|
| H A D | clk-mt8512.c | 17 #define MT8512_PLL_FMAX (3800UL * MHZ)
18 #define MT8512_PLL_FMIN (1500UL * MHZ)
786 .xtal_rate = 26 * MHZ,
787 .xtal2_rate = 26 * MHZ,
|
| H A D | clk-mt8183.c | 18 #define MT8183_PLL_FMAX (3800UL * MHZ)
19 #define MT8183_PLL_FMIN (1500UL * MHZ)
595 .xtal_rate = 26 * MHZ,
596 .xtal2_rate = 26 * MHZ,
|
| H A D | clk-mt7988.c | 813 .xtal_rate = 40 * MHZ,
822 .xtal_rate = 40 * MHZ,
831 .xtal_rate = 40 * MHZ,
|
| H A D | clk-mt8518.c | 17 #define MT8518_PLL_FMAX (3000UL * MHZ)
1491 .xtal_rate = 26 * MHZ,
1492 .xtal2_rate = 26 * MHZ,
|
| /u-boot/arch/arm/mach-imx/imx9/ |
| H A D | clock.c | 652 case MHZ(625):
655 case MHZ(400):
658 case MHZ(333):
661 case MHZ(200):
664 case MHZ(100):
778 set_arm_clk(MHZ(900));
|
| H A D | soc.c | 105 speed = MHZ(2300) - val * MHZ(100);
108 max_speed = MHZ(1700);
|
| /u-boot/arch/m68k/cpu/mcf5445x/ |
| H A D | speed.c | 28 #define MHZ 1000000 macro
|
| /u-boot/arch/arm/mach-imx/imx8ulp/ |
| H A D | clock.c | 171 cgc1_init_core_clk(MHZ(500));
173 cgc1_init_core_clk(MHZ(750));
175 cgc1_init_core_clk(MHZ(960));
|
| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | sdram_common.h | 9 #ifndef MHZ
10 #define MHZ (1000 * 1000) macro
|
| /u-boot/drivers/net/ |
| H A D | sni_netsec.c | 113 #define MHZ(n) ((n) * 1000 * 1000) macro
308 if (freq < MHZ(35))
310 if (freq < MHZ(60))
312 if (freq < MHZ(100))
314 if (freq < MHZ(150))
316 if (freq < MHZ(250))
|
| /u-boot/arch/arm/include/asm/arch-imx8m/ |
| H A D | clock.h | 19 #define MHZ(X) ((X) * 1000000UL) macro
|
| /u-boot/arch/arm/include/asm/arch-imx9/ |
| H A D | clock.h | 13 #define MHZ(x) ((x) * 1000000UL) macro
|
| /u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rk3328.c | 80 u32 mhz = hz / MHZ;
128 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2);
|