1// SPDX-License-Identifier: GPL-2.0 2/* 3 * MediaTek clock driver for MT8518 SoC 4 * 5 * Copyright (C) 2019 BayLibre, SAS 6 * Author: Chen Zhong <chen.zhong@mediatek.com> 7 */ 8 9#include <common.h> 10#include <dm.h> 11#include <asm/io.h> 12#include <dt-bindings/clock/mt8518-clk.h> 13#include <linux/bitops.h> 14 15#include "clk-mtk.h" 16 17#define MT8518_PLL_FMAX (3000UL * MHZ) 18#define MT8518_CON0_RST_BAR BIT(27) 19 20/* apmixedsys */ 21#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ 22 _pd_shift, _pcw_reg, _pcw_shift) { \ 23 .id = _id, \ 24 .reg = _reg, \ 25 .pwr_reg = _pwr_reg, \ 26 .en_mask = _en_mask, \ 27 .rst_bar_mask = MT8518_CON0_RST_BAR, \ 28 .fmax = MT8518_PLL_FMAX, \ 29 .flags = _flags, \ 30 .pcwbits = _pcwbits, \ 31 .pd_reg = _pd_reg, \ 32 .pd_shift = _pd_shift, \ 33 .pcw_reg = _pcw_reg, \ 34 .pcw_shift = _pcw_shift, \ 35 } 36 37static const struct mtk_pll_data apmixed_plls[] = { 38 PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 39 0, 21, 0x0104, 24, 0x0104, 0), 40 PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001, 41 HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0), 42 PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001, 43 HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0), 44 PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 45 0, 21, 0x0164, 24, 0x0164, 0), 46 PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 47 0, 31, 0x0180, 1, 0x0184, 0), 48 PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 49 0, 31, 0x01A0, 1, 0x01A4, 0), 50 PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x00000001, 51 0, 21, 0x01C4, 24, 0x01C4, 0), 52}; 53 54/* topckgen */ 55#define FACTOR0(_id, _parent, _mult, _div) \ 56 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED) 57 58#define FACTOR1(_id, _parent, _mult, _div) \ 59 FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN) 60 61#define FACTOR2(_id, _parent, _mult, _div) \ 62 FACTOR(_id, _parent, _mult, _div, 0) 63 64static const struct mtk_fixed_clk top_fixed_clks[] = { 65 FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000), 66 FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000), 67 FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000), 68 FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000), 69}; 70 71static const struct mtk_fixed_factor top_fixed_divs[] = { 72 FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1), 73 FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4), 74 FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8), 75 FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16), 76 FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11), 77 FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22), 78 FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3), 79 FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6), 80 FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12), 81 FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5), 82 FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10), 83 FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20), 84 FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40), 85 FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7), 86 FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14), 87 FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2), 88 FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4), 89 FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8), 90 FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16), 91 FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3), 92 FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6), 93 FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12), 94 FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24), 95 FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5), 96 FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20), 97 FACTOR0(CLK_TOP_UNIVPLL_D10, CLK_APMIXED_UNIVPLL, 1, 10), 98 FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2), 99 FACTOR0(CLK_TOP_USB20_48M, CLK_APMIXED_UNIVPLL, 1, 26), 100 FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1), 101 FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4), 102 FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1), 103 FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2), 104 FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3), 105 FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4), 106 FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8), 107 FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1), 108 FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2), 109 FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4), 110 FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8), 111 FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793), 112 FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1), 113 FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2), 114 FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4), 115 FACTOR1(CLK_TOP_TVDPLL_D8, CLK_TOP_TVDPLL, 1, 8), 116 FACTOR1(CLK_TOP_TVDPLL_D16, CLK_TOP_TVDPLL, 1, 16), 117 FACTOR1(CLK_TOP_USB20_CLK480M, CLK_TOP_CLK_NULL, 1, 1), 118 FACTOR1(CLK_TOP_RG_APLL1_D2, CLK_TOP_APLL1_SRC_SEL, 1, 2), 119 FACTOR1(CLK_TOP_RG_APLL1_D4, CLK_TOP_APLL1_SRC_SEL, 1, 4), 120 FACTOR1(CLK_TOP_RG_APLL1_D8, CLK_TOP_APLL1_SRC_SEL, 1, 8), 121 FACTOR1(CLK_TOP_RG_APLL1_D16, CLK_TOP_APLL1_SRC_SEL, 1, 16), 122 FACTOR1(CLK_TOP_RG_APLL1_D3, CLK_TOP_APLL1_SRC_SEL, 1, 3), 123 FACTOR1(CLK_TOP_RG_APLL2_D2, CLK_TOP_APLL2_SRC_SEL, 1, 2), 124 FACTOR1(CLK_TOP_RG_APLL2_D4, CLK_TOP_APLL2_SRC_SEL, 1, 4), 125 FACTOR1(CLK_TOP_RG_APLL2_D8, CLK_TOP_APLL2_SRC_SEL, 1, 8), 126 FACTOR1(CLK_TOP_RG_APLL2_D16, CLK_TOP_APLL2_SRC_SEL, 1, 16), 127 FACTOR1(CLK_TOP_RG_APLL2_D3, CLK_TOP_APLL2_SRC_SEL, 1, 3), 128 FACTOR1(CLK_TOP_NFI1X_INFRA_BCLK, CLK_TOP_NFI2X_SEL, 1, 2), 129 FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2), 130}; 131 132static const int uart0_parents[] = { 133 CLK_TOP_CLK26M, 134 CLK_TOP_UNIVPLL_D24 135}; 136 137static const int emi1x_parents[] = { 138 CLK_TOP_CLK26M, 139 CLK_TOP_DMPLL 140}; 141 142static const int emi_ddrphy_parents[] = { 143 CLK_TOP_EMI1X_SEL, 144 CLK_TOP_EMI1X_SEL 145}; 146 147static const int msdc1_parents[] = { 148 CLK_TOP_CLK_NULL, 149 CLK_TOP_CLK26M, 150 CLK_TOP_UNIVPLL_D6, 151 CLK_TOP_CLK_NULL, 152 CLK_TOP_MAINPLL_D8, 153 CLK_TOP_CLK_NULL, 154 CLK_TOP_CLK_NULL, 155 CLK_TOP_CLK_NULL, 156 CLK_TOP_UNIVPLL_D8, 157 CLK_TOP_CLK_NULL, 158 CLK_TOP_CLK_NULL, 159 CLK_TOP_CLK_NULL, 160 CLK_TOP_CLK_NULL, 161 CLK_TOP_CLK_NULL, 162 CLK_TOP_CLK_NULL, 163 CLK_TOP_CLK_NULL, 164 CLK_TOP_MAINPLL_D16, 165 CLK_TOP_CLK_NULL, 166 CLK_TOP_CLK_NULL, 167 CLK_TOP_CLK_NULL, 168 CLK_TOP_CLK_NULL, 169 CLK_TOP_CLK_NULL, 170 CLK_TOP_CLK_NULL, 171 CLK_TOP_CLK_NULL, 172 CLK_TOP_CLK_NULL, 173 CLK_TOP_CLK_NULL, 174 CLK_TOP_CLK_NULL, 175 CLK_TOP_CLK_NULL, 176 CLK_TOP_CLK_NULL, 177 CLK_TOP_CLK_NULL, 178 CLK_TOP_CLK_NULL, 179 CLK_TOP_CLK_NULL, 180 CLK_TOP_MMPLL_D2, 181 CLK_TOP_CLK_NULL, 182 CLK_TOP_CLK_NULL, 183 CLK_TOP_CLK_NULL, 184 CLK_TOP_CLK_NULL, 185 CLK_TOP_CLK_NULL, 186 CLK_TOP_CLK_NULL, 187 CLK_TOP_CLK_NULL, 188 CLK_TOP_CLK_NULL, 189 CLK_TOP_CLK_NULL, 190 CLK_TOP_CLK_NULL, 191 CLK_TOP_CLK_NULL, 192 CLK_TOP_CLK_NULL, 193 CLK_TOP_CLK_NULL, 194 CLK_TOP_CLK_NULL, 195 CLK_TOP_CLK_NULL, 196 CLK_TOP_CLK_NULL, 197 CLK_TOP_CLK_NULL, 198 CLK_TOP_CLK_NULL, 199 CLK_TOP_CLK_NULL, 200 CLK_TOP_CLK_NULL, 201 CLK_TOP_CLK_NULL, 202 CLK_TOP_CLK_NULL, 203 CLK_TOP_CLK_NULL, 204 CLK_TOP_CLK_NULL, 205 CLK_TOP_CLK_NULL, 206 CLK_TOP_CLK_NULL, 207 CLK_TOP_CLK_NULL, 208 CLK_TOP_CLK_NULL, 209 CLK_TOP_CLK_NULL, 210 CLK_TOP_CLK_NULL, 211 CLK_TOP_CLK_NULL, 212 CLK_TOP_MAINPLL_D12 213}; 214 215static const int pwm_mm_parents[] = { 216 CLK_TOP_CLK26M, 217 CLK_TOP_UNIVPLL_D12 218}; 219 220static const int pmicspi_parents[] = { 221 CLK_TOP_UNIVPLL_D20, 222 CLK_TOP_USB20_48M, 223 CLK_TOP_UNIVPLL_D16, 224 CLK_TOP_CLK26M, 225 CLK_TOP_CLK26M_D2 226}; 227 228static const int nfi2x_parents[] = { 229 CLK_TOP_CLK26M, 230 CLK_TOP_MAINPLL_D4, 231 CLK_TOP_MAINPLL_D5, 232 CLK_TOP_MAINPLL_D6, 233 CLK_TOP_MAINPLL_D7, 234 CLK_TOP_MAINPLL_D8, 235 CLK_TOP_MAINPLL_D10, 236 CLK_TOP_MAINPLL_D12 237}; 238 239static const int ddrphycfg_parents[] = { 240 CLK_TOP_CLK26M, 241 CLK_TOP_MAINPLL_D16 242}; 243 244static const int smi_parents[] = { 245 CLK_TOP_CLK_NULL, 246 CLK_TOP_CLK26M, 247 CLK_TOP_CLK_NULL, 248 CLK_TOP_CLK_NULL, 249 CLK_TOP_CLK_NULL, 250 CLK_TOP_CLK_NULL, 251 CLK_TOP_CLK_NULL, 252 CLK_TOP_CLK_NULL, 253 CLK_TOP_CLK_NULL, 254 CLK_TOP_UNIVPLL_D4, 255 CLK_TOP_MAINPLL_D7, 256 CLK_TOP_CLK_NULL, 257 CLK_TOP_MAINPLL_D14 258}; 259 260static const int usb_parents[] = { 261 CLK_TOP_CLK_NULL, 262 CLK_TOP_CLK26M, 263 CLK_TOP_UNIVPLL_D16, 264 CLK_TOP_CLK_NULL, 265 CLK_TOP_MAINPLL_D20 266}; 267 268static const int spinor_parents[] = { 269 CLK_TOP_CLK26M_D2, 270 CLK_TOP_CLK26M, 271 CLK_TOP_MAINPLL_D40, 272 CLK_TOP_UNIVPLL_D24, 273 CLK_TOP_UNIVPLL_D20, 274 CLK_TOP_MAINPLL_D20, 275 CLK_TOP_MAINPLL_D16, 276 CLK_TOP_UNIVPLL_D12 277}; 278 279static const int eth_parents[] = { 280 CLK_TOP_CLK26M, 281 CLK_TOP_MAINPLL_D40, 282 CLK_TOP_UNIVPLL_D24, 283 CLK_TOP_UNIVPLL_D20, 284 CLK_TOP_MAINPLL_D20 285}; 286 287static const int aud1_parents[] = { 288 CLK_TOP_CLK26M, 289 CLK_TOP_APLL1_SRC_SEL 290}; 291 292static const int aud2_parents[] = { 293 CLK_TOP_CLK26M, 294 CLK_TOP_APLL2_SRC_SEL 295}; 296 297static const int i2c_parents[] = { 298 CLK_TOP_CLK26M, 299 CLK_TOP_USB20_48M, 300 CLK_TOP_UNIVPLL_D12, 301 CLK_TOP_UNIVPLL_D10, 302 CLK_TOP_UNIVPLL_D8 303}; 304 305static const int aud_i2s0_m_parents[] = { 306 CLK_TOP_AUD1, 307 CLK_TOP_AUD2 308}; 309 310static const int aud_spdifin_parents[] = { 311 CLK_TOP_CLK26M, 312 CLK_TOP_UNIVPLL_D2, 313 CLK_TOP_TVDPLL 314}; 315 316static const int dbg_atclk_parents[] = { 317 CLK_TOP_CLK_NULL, 318 CLK_TOP_CLK26M, 319 CLK_TOP_MAINPLL_D5, 320 CLK_TOP_CLK_NULL, 321 CLK_TOP_UNIVPLL_D5 322}; 323 324static const int png_sys_parents[] = { 325 CLK_TOP_CLK26M, 326 CLK_TOP_UNIVPLL_D8, 327 CLK_TOP_MAINPLL_D7, 328 CLK_TOP_MAINPLL_D6, 329 CLK_TOP_MAINPLL_D5, 330 CLK_TOP_UNIVPLL_D3 331}; 332 333static const int sej_13m_parents[] = { 334 CLK_TOP_CLK26M, 335 CLK_TOP_CLK26M_D2 336}; 337 338static const int imgrz_sys_parents[] = { 339 CLK_TOP_CLK26M, 340 CLK_TOP_MAINPLL_D6, 341 CLK_TOP_MAINPLL_D7, 342 CLK_TOP_MAINPLL_D5, 343 CLK_TOP_UNIVPLL_D4, 344 CLK_TOP_UNIVPLL_D10, 345 CLK_TOP_UNIVPLL_D5, 346 CLK_TOP_UNIVPLL_D6 347}; 348 349static const int graph_eclk_parents[] = { 350 CLK_TOP_CLK26M, 351 CLK_TOP_MAINPLL_D6, 352 CLK_TOP_UNIVPLL_D8, 353 CLK_TOP_UNIVPLL_D16, 354 CLK_TOP_MAINPLL_D7, 355 CLK_TOP_UNIVPLL_D4, 356 CLK_TOP_UNIVPLL_D10, 357 CLK_TOP_UNIVPLL_D24, 358 CLK_TOP_MAINPLL_D8 359}; 360 361static const int fdbi_parents[] = { 362 CLK_TOP_CLK26M, 363 CLK_TOP_MAINPLL_D12, 364 CLK_TOP_MAINPLL_D14, 365 CLK_TOP_MAINPLL_D16, 366 CLK_TOP_UNIVPLL_D10, 367 CLK_TOP_UNIVPLL_D12, 368 CLK_TOP_UNIVPLL_D16, 369 CLK_TOP_UNIVPLL_D24, 370 CLK_TOP_TVDPLL_D2, 371 CLK_TOP_TVDPLL_D4, 372 CLK_TOP_TVDPLL_D8, 373 CLK_TOP_TVDPLL_D16 374}; 375 376static const int faudio_parents[] = { 377 CLK_TOP_CLK26M, 378 CLK_TOP_UNIVPLL_D24, 379 CLK_TOP_APLL1_D4, 380 CLK_TOP_APLL2_D4 381}; 382 383static const int fa2sys_parents[] = { 384 CLK_TOP_CLK26M, 385 CLK_TOP_APLL1_SRC_SEL, 386 CLK_TOP_RG_APLL1_D2, 387 CLK_TOP_RG_APLL1_D4, 388 CLK_TOP_RG_APLL1_D8, 389 CLK_TOP_RG_APLL1_D16, 390 CLK_TOP_CLK26M_D2, 391 CLK_TOP_RG_APLL1_D3 392}; 393 394static const int fa1sys_parents[] = { 395 CLK_TOP_CLK26M, 396 CLK_TOP_APLL2_SRC_SEL, 397 CLK_TOP_RG_APLL2_D2, 398 CLK_TOP_RG_APLL2_D4, 399 CLK_TOP_RG_APLL2_D8, 400 CLK_TOP_RG_APLL2_D16, 401 CLK_TOP_CLK26M_D2, 402 CLK_TOP_RG_APLL2_D3 403}; 404 405static const int fasm_m_parents[] = { 406 CLK_TOP_CLK26M, 407 CLK_TOP_UNIVPLL_D12, 408 CLK_TOP_UNIVPLL_D6, 409 CLK_TOP_MAINPLL_D7 410}; 411 412static const int fecc_ck_parents[] = { 413 CLK_TOP_CLK_NULL, 414 CLK_TOP_CLK_NULL, 415 CLK_TOP_CLK_NULL, 416 CLK_TOP_CLK_NULL, 417 CLK_TOP_CLK_NULL, 418 CLK_TOP_CLK_NULL, 419 CLK_TOP_CLK_NULL, 420 CLK_TOP_CLK_NULL, 421 CLK_TOP_CLK_NULL, 422 CLK_TOP_CLK26M, 423 CLK_TOP_UNIVPLL_D6, 424 CLK_TOP_CLK_NULL, 425 CLK_TOP_UNIVPLL_D4, 426 CLK_TOP_CLK_NULL, 427 CLK_TOP_CLK_NULL, 428 CLK_TOP_CLK_NULL, 429 CLK_TOP_UNIVPLL_D3, 430 CLK_TOP_CLK_NULL, 431 CLK_TOP_CLK_NULL, 432 CLK_TOP_CLK_NULL, 433 CLK_TOP_CLK_NULL, 434 CLK_TOP_CLK_NULL, 435 CLK_TOP_CLK_NULL, 436 CLK_TOP_CLK_NULL, 437 CLK_TOP_CLK_NULL, 438 CLK_TOP_CLK_NULL, 439 CLK_TOP_CLK_NULL, 440 CLK_TOP_CLK_NULL, 441 CLK_TOP_CLK_NULL, 442 CLK_TOP_CLK_NULL, 443 CLK_TOP_CLK_NULL, 444 CLK_TOP_CLK_NULL, 445 CLK_TOP_MAINPLL_D3 446}; 447 448static const int pe2_mac_parents[] = { 449 CLK_TOP_CLK26M, 450 CLK_TOP_MAINPLL_D11, 451 CLK_TOP_MAINPLL_D16, 452 CLK_TOP_UNIVPLL_D12, 453 CLK_TOP_UNIVPLL_D10 454}; 455 456static const int cmsys_parents[] = { 457 CLK_TOP_CLK26M, 458 CLK_TOP_UNIVPLL_D5, 459 CLK_TOP_UNIVPLL_D6, 460 CLK_TOP_MAINPLL_D5, 461 CLK_TOP_APLL2, 462 CLK_TOP_APLL2_D2, 463 CLK_TOP_APLL2_D4, 464 CLK_TOP_APLL2_D3 465}; 466 467static const int gcpu_parents[] = { 468 CLK_TOP_CLK26M, 469 CLK_TOP_MAINPLL_D4, 470 CLK_TOP_MAINPLL_D5, 471 CLK_TOP_MAINPLL_D6, 472 CLK_TOP_MAINPLL_D7, 473 CLK_TOP_UNIVPLL_D4, 474 CLK_TOP_UNIVPLL_D10, 475 CLK_TOP_UNIVPLL_D3 476}; 477 478static const int spis_ck_parents[] = { 479 CLK_TOP_CLK_NULL, 480 CLK_TOP_CLK26M, 481 CLK_TOP_UNIVPLL_D12, 482 CLK_TOP_CLK_NULL, 483 CLK_TOP_UNIVPLL_D8, 484 CLK_TOP_CLK_NULL, 485 CLK_TOP_CLK_NULL, 486 CLK_TOP_CLK_NULL, 487 CLK_TOP_UNIVPLL_D6, 488 CLK_TOP_CLK_NULL, 489 CLK_TOP_CLK_NULL, 490 CLK_TOP_CLK_NULL, 491 CLK_TOP_CLK_NULL, 492 CLK_TOP_CLK_NULL, 493 CLK_TOP_CLK_NULL, 494 CLK_TOP_CLK_NULL, 495 CLK_TOP_UNIVPLL_D5, 496 CLK_TOP_CLK_NULL, 497 CLK_TOP_CLK_NULL, 498 CLK_TOP_CLK_NULL, 499 CLK_TOP_CLK_NULL, 500 CLK_TOP_CLK_NULL, 501 CLK_TOP_CLK_NULL, 502 CLK_TOP_CLK_NULL, 503 CLK_TOP_CLK_NULL, 504 CLK_TOP_CLK_NULL, 505 CLK_TOP_CLK_NULL, 506 CLK_TOP_CLK_NULL, 507 CLK_TOP_CLK_NULL, 508 CLK_TOP_CLK_NULL, 509 CLK_TOP_CLK_NULL, 510 CLK_TOP_CLK_NULL, 511 CLK_TOP_UNIVPLL_D4, 512 CLK_TOP_CLK_NULL, 513 CLK_TOP_CLK_NULL, 514 CLK_TOP_CLK_NULL, 515 CLK_TOP_CLK_NULL, 516 CLK_TOP_CLK_NULL, 517 CLK_TOP_CLK_NULL, 518 CLK_TOP_CLK_NULL, 519 CLK_TOP_CLK_NULL, 520 CLK_TOP_CLK_NULL, 521 CLK_TOP_CLK_NULL, 522 CLK_TOP_CLK_NULL, 523 CLK_TOP_CLK_NULL, 524 CLK_TOP_CLK_NULL, 525 CLK_TOP_CLK_NULL, 526 CLK_TOP_CLK_NULL, 527 CLK_TOP_CLK_NULL, 528 CLK_TOP_CLK_NULL, 529 CLK_TOP_CLK_NULL, 530 CLK_TOP_CLK_NULL, 531 CLK_TOP_CLK_NULL, 532 CLK_TOP_CLK_NULL, 533 CLK_TOP_CLK_NULL, 534 CLK_TOP_CLK_NULL, 535 CLK_TOP_CLK_NULL, 536 CLK_TOP_CLK_NULL, 537 CLK_TOP_CLK_NULL, 538 CLK_TOP_CLK_NULL, 539 CLK_TOP_CLK_NULL, 540 CLK_TOP_CLK_NULL, 541 CLK_TOP_CLK_NULL, 542 CLK_TOP_CLK_NULL, 543 CLK_TOP_MAINPLL_D4, 544 CLK_TOP_CLK_NULL, 545 CLK_TOP_CLK_NULL, 546 CLK_TOP_CLK_NULL, 547 CLK_TOP_CLK_NULL, 548 CLK_TOP_CLK_NULL, 549 CLK_TOP_CLK_NULL, 550 CLK_TOP_CLK_NULL, 551 CLK_TOP_CLK_NULL, 552 CLK_TOP_CLK_NULL, 553 CLK_TOP_CLK_NULL, 554 CLK_TOP_CLK_NULL, 555 CLK_TOP_CLK_NULL, 556 CLK_TOP_CLK_NULL, 557 CLK_TOP_CLK_NULL, 558 CLK_TOP_CLK_NULL, 559 CLK_TOP_CLK_NULL, 560 CLK_TOP_CLK_NULL, 561 CLK_TOP_CLK_NULL, 562 CLK_TOP_CLK_NULL, 563 CLK_TOP_CLK_NULL, 564 CLK_TOP_CLK_NULL, 565 CLK_TOP_CLK_NULL, 566 CLK_TOP_CLK_NULL, 567 CLK_TOP_CLK_NULL, 568 CLK_TOP_CLK_NULL, 569 CLK_TOP_CLK_NULL, 570 CLK_TOP_CLK_NULL, 571 CLK_TOP_CLK_NULL, 572 CLK_TOP_CLK_NULL, 573 CLK_TOP_CLK_NULL, 574 CLK_TOP_CLK_NULL, 575 CLK_TOP_CLK_NULL, 576 CLK_TOP_CLK_NULL, 577 CLK_TOP_CLK_NULL, 578 CLK_TOP_CLK_NULL, 579 CLK_TOP_CLK_NULL, 580 CLK_TOP_CLK_NULL, 581 CLK_TOP_CLK_NULL, 582 CLK_TOP_CLK_NULL, 583 CLK_TOP_CLK_NULL, 584 CLK_TOP_CLK_NULL, 585 CLK_TOP_CLK_NULL, 586 CLK_TOP_CLK_NULL, 587 CLK_TOP_CLK_NULL, 588 CLK_TOP_CLK_NULL, 589 CLK_TOP_CLK_NULL, 590 CLK_TOP_CLK_NULL, 591 CLK_TOP_CLK_NULL, 592 CLK_TOP_CLK_NULL, 593 CLK_TOP_CLK_NULL, 594 CLK_TOP_CLK_NULL, 595 CLK_TOP_CLK_NULL, 596 CLK_TOP_CLK_NULL, 597 CLK_TOP_CLK_NULL, 598 CLK_TOP_CLK_NULL, 599 CLK_TOP_CLK_NULL, 600 CLK_TOP_CLK_NULL, 601 CLK_TOP_CLK_NULL, 602 CLK_TOP_CLK_NULL, 603 CLK_TOP_CLK_NULL, 604 CLK_TOP_CLK_NULL, 605 CLK_TOP_CLK_NULL, 606 CLK_TOP_CLK_NULL, 607 CLK_TOP_UNIVPLL_D3 608}; 609 610static const int apll1_ref_parents[] = { 611 CLK_TOP_CLK_NULL, 612 CLK_TOP_CLK_NULL, 613 CLK_TOP_CLK_NULL, 614 CLK_TOP_CLK_NULL, 615 CLK_TOP_CLK_NULL, 616 CLK_TOP_CLK_NULL 617}; 618 619static const int int_32k_parents[] = { 620 CLK_TOP_CLK32K, 621 CLK_TOP_CLK26M_D793 622}; 623 624static const int apll1_src_parents[] = { 625 CLK_TOP_APLL1, 626 CLK_TOP_CLK_NULL, 627 CLK_TOP_CLK_NULL, 628 CLK_TOP_CLK_NULL 629}; 630 631static const int apll2_src_parents[] = { 632 CLK_TOP_APLL2, 633 CLK_TOP_CLK_NULL, 634 CLK_TOP_CLK_NULL, 635 CLK_TOP_CLK_NULL 636}; 637 638static const int faud_intbus_parents[] = { 639 CLK_TOP_CLK_NULL, 640 CLK_TOP_CLK26M, 641 CLK_TOP_MAINPLL_D11, 642 CLK_TOP_CLK_NULL, 643 CLK_TOP_CLK26M, 644 CLK_TOP_CLK_NULL, 645 CLK_TOP_CLK_NULL, 646 CLK_TOP_CLK_NULL, 647 CLK_TOP_UNIVPLL_D10, 648 CLK_TOP_CLK_NULL, 649 CLK_TOP_CLK_NULL, 650 CLK_TOP_CLK_NULL, 651 CLK_TOP_CLK_NULL, 652 CLK_TOP_CLK_NULL, 653 CLK_TOP_CLK_NULL, 654 CLK_TOP_CLK_NULL, 655 CLK_TOP_RG_APLL2_D8, 656 CLK_TOP_CLK_NULL, 657 CLK_TOP_CLK_NULL, 658 CLK_TOP_CLK_NULL, 659 CLK_TOP_CLK_NULL, 660 CLK_TOP_CLK_NULL, 661 CLK_TOP_CLK_NULL, 662 CLK_TOP_CLK_NULL, 663 CLK_TOP_CLK_NULL, 664 CLK_TOP_CLK_NULL, 665 CLK_TOP_CLK_NULL, 666 CLK_TOP_CLK_NULL, 667 CLK_TOP_CLK_NULL, 668 CLK_TOP_CLK_NULL, 669 CLK_TOP_CLK_NULL, 670 CLK_TOP_CLK_NULL, 671 CLK_TOP_CLK26M_D2, 672 CLK_TOP_CLK_NULL, 673 CLK_TOP_CLK_NULL, 674 CLK_TOP_CLK_NULL, 675 CLK_TOP_CLK_NULL, 676 CLK_TOP_CLK_NULL, 677 CLK_TOP_CLK_NULL, 678 CLK_TOP_CLK_NULL, 679 CLK_TOP_CLK_NULL, 680 CLK_TOP_CLK_NULL, 681 CLK_TOP_CLK_NULL, 682 CLK_TOP_CLK_NULL, 683 CLK_TOP_CLK_NULL, 684 CLK_TOP_CLK_NULL, 685 CLK_TOP_CLK_NULL, 686 CLK_TOP_CLK_NULL, 687 CLK_TOP_CLK_NULL, 688 CLK_TOP_CLK_NULL, 689 CLK_TOP_CLK_NULL, 690 CLK_TOP_CLK_NULL, 691 CLK_TOP_CLK_NULL, 692 CLK_TOP_CLK_NULL, 693 CLK_TOP_CLK_NULL, 694 CLK_TOP_CLK_NULL, 695 CLK_TOP_CLK_NULL, 696 CLK_TOP_CLK_NULL, 697 CLK_TOP_CLK_NULL, 698 CLK_TOP_CLK_NULL, 699 CLK_TOP_CLK_NULL, 700 CLK_TOP_CLK_NULL, 701 CLK_TOP_CLK_NULL, 702 CLK_TOP_CLK_NULL, 703 CLK_TOP_RG_APLL1_D8, 704 CLK_TOP_CLK_NULL, 705 CLK_TOP_CLK_NULL, 706 CLK_TOP_CLK_NULL, 707 CLK_TOP_CLK_NULL, 708 CLK_TOP_CLK_NULL, 709 CLK_TOP_CLK_NULL, 710 CLK_TOP_CLK_NULL, 711 CLK_TOP_CLK_NULL, 712 CLK_TOP_CLK_NULL, 713 CLK_TOP_CLK_NULL, 714 CLK_TOP_CLK_NULL, 715 CLK_TOP_CLK_NULL, 716 CLK_TOP_CLK_NULL, 717 CLK_TOP_CLK_NULL, 718 CLK_TOP_CLK_NULL, 719 CLK_TOP_CLK_NULL, 720 CLK_TOP_CLK_NULL, 721 CLK_TOP_CLK_NULL, 722 CLK_TOP_CLK_NULL, 723 CLK_TOP_CLK_NULL, 724 CLK_TOP_CLK_NULL, 725 CLK_TOP_CLK_NULL, 726 CLK_TOP_CLK_NULL, 727 CLK_TOP_CLK_NULL, 728 CLK_TOP_CLK_NULL, 729 CLK_TOP_CLK_NULL, 730 CLK_TOP_CLK_NULL, 731 CLK_TOP_CLK_NULL, 732 CLK_TOP_CLK_NULL, 733 CLK_TOP_CLK_NULL, 734 CLK_TOP_CLK_NULL, 735 CLK_TOP_CLK_NULL, 736 CLK_TOP_CLK_NULL, 737 CLK_TOP_CLK_NULL, 738 CLK_TOP_CLK_NULL, 739 CLK_TOP_CLK_NULL, 740 CLK_TOP_CLK_NULL, 741 CLK_TOP_CLK_NULL, 742 CLK_TOP_CLK_NULL, 743 CLK_TOP_CLK_NULL, 744 CLK_TOP_CLK_NULL, 745 CLK_TOP_CLK_NULL, 746 CLK_TOP_CLK_NULL, 747 CLK_TOP_CLK_NULL, 748 CLK_TOP_CLK_NULL, 749 CLK_TOP_CLK_NULL, 750 CLK_TOP_CLK_NULL, 751 CLK_TOP_CLK_NULL, 752 CLK_TOP_CLK_NULL, 753 CLK_TOP_CLK_NULL, 754 CLK_TOP_CLK_NULL, 755 CLK_TOP_CLK_NULL, 756 CLK_TOP_CLK_NULL, 757 CLK_TOP_CLK_NULL, 758 CLK_TOP_CLK_NULL, 759 CLK_TOP_CLK_NULL, 760 CLK_TOP_CLK_NULL, 761 CLK_TOP_CLK_NULL, 762 CLK_TOP_CLK_NULL, 763 CLK_TOP_CLK_NULL, 764 CLK_TOP_CLK_NULL, 765 CLK_TOP_CLK_NULL, 766 CLK_TOP_CLK_NULL, 767 CLK_TOP_UNIVPLL_D20 768}; 769 770static const int axibus_parents[] = { 771 CLK_TOP_CLK_NULL, 772 CLK_TOP_CLK26M, 773 CLK_TOP_MAINPLL_D11, 774 CLK_TOP_CLK_NULL, 775 CLK_TOP_MAINPLL_D12, 776 CLK_TOP_CLK_NULL, 777 CLK_TOP_CLK_NULL, 778 CLK_TOP_CLK_NULL, 779 CLK_TOP_UNIVPLL_D10, 780 CLK_TOP_CLK_NULL, 781 CLK_TOP_CLK_NULL, 782 CLK_TOP_CLK_NULL, 783 CLK_TOP_CLK_NULL, 784 CLK_TOP_CLK_NULL, 785 CLK_TOP_CLK_NULL, 786 CLK_TOP_CLK_NULL, 787 CLK_TOP_CLK26M_D2, 788 CLK_TOP_CLK_NULL, 789 CLK_TOP_CLK_NULL, 790 CLK_TOP_CLK_NULL, 791 CLK_TOP_CLK_NULL, 792 CLK_TOP_CLK_NULL, 793 CLK_TOP_CLK_NULL, 794 CLK_TOP_CLK_NULL, 795 CLK_TOP_CLK_NULL, 796 CLK_TOP_CLK_NULL, 797 CLK_TOP_CLK_NULL, 798 CLK_TOP_CLK_NULL, 799 CLK_TOP_CLK_NULL, 800 CLK_TOP_CLK_NULL, 801 CLK_TOP_CLK_NULL, 802 CLK_TOP_CLK_NULL, 803 CLK_TOP_APLL2_D8 804}; 805 806static const int hapll1_parents[] = { 807 CLK_TOP_CLK26M, 808 CLK_TOP_APLL1_SRC_SEL, 809 CLK_TOP_RG_APLL1_D2, 810 CLK_TOP_RG_APLL1_D4, 811 CLK_TOP_RG_APLL1_D8, 812 CLK_TOP_RG_APLL1_D16, 813 CLK_TOP_CLK26M_D2, 814 CLK_TOP_CLK26M_D8, 815 CLK_TOP_RG_APLL1_D3 816}; 817 818static const int hapll2_parents[] = { 819 CLK_TOP_CLK26M, 820 CLK_TOP_APLL2_SRC_SEL, 821 CLK_TOP_RG_APLL2_D2, 822 CLK_TOP_RG_APLL2_D4, 823 CLK_TOP_RG_APLL2_D8, 824 CLK_TOP_RG_APLL2_D16, 825 CLK_TOP_CLK26M_D2, 826 CLK_TOP_CLK26M_D4, 827 CLK_TOP_RG_APLL2_D3 828}; 829 830static const int spinfi_parents[] = { 831 CLK_TOP_CLK26M, 832 CLK_TOP_UNIVPLL_D24, 833 CLK_TOP_UNIVPLL_D20, 834 CLK_TOP_MAINPLL_D22, 835 CLK_TOP_UNIVPLL_D16, 836 CLK_TOP_MAINPLL_D16, 837 CLK_TOP_UNIVPLL_D12, 838 CLK_TOP_UNIVPLL_D10, 839 CLK_TOP_MAINPLL_D11 840}; 841 842static const int msdc0_parents[] = { 843 CLK_TOP_CLK_NULL, 844 CLK_TOP_CLK26M, 845 CLK_TOP_UNIVPLL_D6, 846 CLK_TOP_CLK_NULL, 847 CLK_TOP_MAINPLL_D8, 848 CLK_TOP_CLK_NULL, 849 CLK_TOP_CLK_NULL, 850 CLK_TOP_CLK_NULL, 851 CLK_TOP_UNIVPLL_D8, 852 CLK_TOP_CLK_NULL, 853 CLK_TOP_CLK_NULL, 854 CLK_TOP_CLK_NULL, 855 CLK_TOP_CLK_NULL, 856 CLK_TOP_CLK_NULL, 857 CLK_TOP_CLK_NULL, 858 CLK_TOP_CLK_NULL, 859 CLK_TOP_MAINPLL_D16, 860 CLK_TOP_CLK_NULL, 861 CLK_TOP_CLK_NULL, 862 CLK_TOP_CLK_NULL, 863 CLK_TOP_CLK_NULL, 864 CLK_TOP_CLK_NULL, 865 CLK_TOP_CLK_NULL, 866 CLK_TOP_CLK_NULL, 867 CLK_TOP_CLK_NULL, 868 CLK_TOP_CLK_NULL, 869 CLK_TOP_CLK_NULL, 870 CLK_TOP_CLK_NULL, 871 CLK_TOP_CLK_NULL, 872 CLK_TOP_CLK_NULL, 873 CLK_TOP_CLK_NULL, 874 CLK_TOP_CLK_NULL, 875 CLK_TOP_MAINPLL_D12, 876 CLK_TOP_CLK_NULL, 877 CLK_TOP_CLK_NULL, 878 CLK_TOP_CLK_NULL, 879 CLK_TOP_CLK_NULL, 880 CLK_TOP_CLK_NULL, 881 CLK_TOP_CLK_NULL, 882 CLK_TOP_CLK_NULL, 883 CLK_TOP_CLK_NULL, 884 CLK_TOP_CLK_NULL, 885 CLK_TOP_CLK_NULL, 886 CLK_TOP_CLK_NULL, 887 CLK_TOP_CLK_NULL, 888 CLK_TOP_CLK_NULL, 889 CLK_TOP_CLK_NULL, 890 CLK_TOP_CLK_NULL, 891 CLK_TOP_CLK_NULL, 892 CLK_TOP_CLK_NULL, 893 CLK_TOP_CLK_NULL, 894 CLK_TOP_CLK_NULL, 895 CLK_TOP_CLK_NULL, 896 CLK_TOP_CLK_NULL, 897 CLK_TOP_CLK_NULL, 898 CLK_TOP_CLK_NULL, 899 CLK_TOP_CLK_NULL, 900 CLK_TOP_CLK_NULL, 901 CLK_TOP_CLK_NULL, 902 CLK_TOP_CLK_NULL, 903 CLK_TOP_CLK_NULL, 904 CLK_TOP_CLK_NULL, 905 CLK_TOP_CLK_NULL, 906 CLK_TOP_CLK_NULL, 907 CLK_APMIXED_MMPLL, 908 CLK_TOP_CLK_NULL, 909 CLK_TOP_CLK_NULL, 910 CLK_TOP_CLK_NULL, 911 CLK_TOP_CLK_NULL, 912 CLK_TOP_CLK_NULL, 913 CLK_TOP_CLK_NULL, 914 CLK_TOP_CLK_NULL, 915 CLK_TOP_CLK_NULL, 916 CLK_TOP_CLK_NULL, 917 CLK_TOP_CLK_NULL, 918 CLK_TOP_CLK_NULL, 919 CLK_TOP_CLK_NULL, 920 CLK_TOP_CLK_NULL, 921 CLK_TOP_CLK_NULL, 922 CLK_TOP_CLK_NULL, 923 CLK_TOP_CLK_NULL, 924 CLK_TOP_CLK_NULL, 925 CLK_TOP_CLK_NULL, 926 CLK_TOP_CLK_NULL, 927 CLK_TOP_CLK_NULL, 928 CLK_TOP_CLK_NULL, 929 CLK_TOP_CLK_NULL, 930 CLK_TOP_CLK_NULL, 931 CLK_TOP_CLK_NULL, 932 CLK_TOP_CLK_NULL, 933 CLK_TOP_CLK_NULL, 934 CLK_TOP_CLK_NULL, 935 CLK_TOP_CLK_NULL, 936 CLK_TOP_CLK_NULL, 937 CLK_TOP_CLK_NULL, 938 CLK_TOP_CLK_NULL, 939 CLK_TOP_CLK_NULL, 940 CLK_TOP_CLK_NULL, 941 CLK_TOP_CLK_NULL, 942 CLK_TOP_CLK_NULL, 943 CLK_TOP_CLK_NULL, 944 CLK_TOP_CLK_NULL, 945 CLK_TOP_CLK_NULL, 946 CLK_TOP_CLK_NULL, 947 CLK_TOP_CLK_NULL, 948 CLK_TOP_CLK_NULL, 949 CLK_TOP_CLK_NULL, 950 CLK_TOP_CLK_NULL, 951 CLK_TOP_CLK_NULL, 952 CLK_TOP_CLK_NULL, 953 CLK_TOP_CLK_NULL, 954 CLK_TOP_CLK_NULL, 955 CLK_TOP_CLK_NULL, 956 CLK_TOP_CLK_NULL, 957 CLK_TOP_CLK_NULL, 958 CLK_TOP_CLK_NULL, 959 CLK_TOP_CLK_NULL, 960 CLK_TOP_CLK_NULL, 961 CLK_TOP_CLK_NULL, 962 CLK_TOP_CLK_NULL, 963 CLK_TOP_CLK_NULL, 964 CLK_TOP_CLK_NULL, 965 CLK_TOP_CLK_NULL, 966 CLK_TOP_CLK_NULL, 967 CLK_TOP_CLK_NULL, 968 CLK_TOP_CLK_NULL, 969 CLK_TOP_CLK_NULL, 970 CLK_TOP_CLK_NULL, 971 CLK_TOP_MMPLL_D2 972}; 973 974static const int msdc0_clk50_parents[] = { 975 CLK_TOP_CLK_NULL, 976 CLK_TOP_CLK_NULL, 977 CLK_TOP_CLK_NULL, 978 CLK_TOP_CLK_NULL, 979 CLK_TOP_CLK_NULL, 980 CLK_TOP_CLK_NULL, 981 CLK_TOP_CLK_NULL, 982 CLK_TOP_CLK_NULL, 983 CLK_TOP_CLK_NULL, 984 CLK_TOP_CLK26M, 985 CLK_TOP_UNIVPLL_D6, 986 CLK_TOP_CLK_NULL, 987 CLK_TOP_MAINPLL_D8, 988 CLK_TOP_CLK_NULL, 989 CLK_TOP_CLK_NULL, 990 CLK_TOP_CLK_NULL, 991 CLK_TOP_UNIVPLL_D8, 992 CLK_TOP_CLK_NULL, 993 CLK_TOP_CLK_NULL, 994 CLK_TOP_CLK_NULL, 995 CLK_TOP_CLK_NULL, 996 CLK_TOP_CLK_NULL, 997 CLK_TOP_CLK_NULL, 998 CLK_TOP_CLK_NULL, 999 CLK_TOP_CLK_NULL, 1000 CLK_TOP_CLK_NULL, 1001 CLK_TOP_CLK_NULL, 1002 CLK_TOP_CLK_NULL, 1003 CLK_TOP_CLK_NULL, 1004 CLK_TOP_CLK_NULL, 1005 CLK_TOP_CLK_NULL, 1006 CLK_TOP_CLK_NULL, 1007 CLK_TOP_MAINPLL_D6 1008}; 1009 1010static const int msdc2_parents[] = { 1011 CLK_TOP_CLK_NULL, 1012 CLK_TOP_CLK26M, 1013 CLK_TOP_UNIVPLL_D6, 1014 CLK_TOP_CLK_NULL, 1015 CLK_TOP_MAINPLL_D8, 1016 CLK_TOP_CLK_NULL, 1017 CLK_TOP_CLK_NULL, 1018 CLK_TOP_CLK_NULL, 1019 CLK_TOP_UNIVPLL_D8, 1020 CLK_TOP_CLK_NULL, 1021 CLK_TOP_CLK_NULL, 1022 CLK_TOP_CLK_NULL, 1023 CLK_TOP_CLK_NULL, 1024 CLK_TOP_CLK_NULL, 1025 CLK_TOP_CLK_NULL, 1026 CLK_TOP_CLK_NULL, 1027 CLK_TOP_MAINPLL_D16, 1028 CLK_TOP_CLK_NULL, 1029 CLK_TOP_CLK_NULL, 1030 CLK_TOP_CLK_NULL, 1031 CLK_TOP_CLK_NULL, 1032 CLK_TOP_CLK_NULL, 1033 CLK_TOP_CLK_NULL, 1034 CLK_TOP_CLK_NULL, 1035 CLK_TOP_CLK_NULL, 1036 CLK_TOP_CLK_NULL, 1037 CLK_TOP_CLK_NULL, 1038 CLK_TOP_CLK_NULL, 1039 CLK_TOP_CLK_NULL, 1040 CLK_TOP_CLK_NULL, 1041 CLK_TOP_CLK_NULL, 1042 CLK_TOP_CLK_NULL, 1043 CLK_TOP_MMPLL_D2, 1044 CLK_TOP_CLK_NULL, 1045 CLK_TOP_CLK_NULL, 1046 CLK_TOP_CLK_NULL, 1047 CLK_TOP_CLK_NULL, 1048 CLK_TOP_CLK_NULL, 1049 CLK_TOP_CLK_NULL, 1050 CLK_TOP_CLK_NULL, 1051 CLK_TOP_CLK_NULL, 1052 CLK_TOP_CLK_NULL, 1053 CLK_TOP_CLK_NULL, 1054 CLK_TOP_CLK_NULL, 1055 CLK_TOP_CLK_NULL, 1056 CLK_TOP_CLK_NULL, 1057 CLK_TOP_CLK_NULL, 1058 CLK_TOP_CLK_NULL, 1059 CLK_TOP_CLK_NULL, 1060 CLK_TOP_CLK_NULL, 1061 CLK_TOP_CLK_NULL, 1062 CLK_TOP_CLK_NULL, 1063 CLK_TOP_CLK_NULL, 1064 CLK_TOP_CLK_NULL, 1065 CLK_TOP_CLK_NULL, 1066 CLK_TOP_CLK_NULL, 1067 CLK_TOP_CLK_NULL, 1068 CLK_TOP_CLK_NULL, 1069 CLK_TOP_CLK_NULL, 1070 CLK_TOP_CLK_NULL, 1071 CLK_TOP_CLK_NULL, 1072 CLK_TOP_CLK_NULL, 1073 CLK_TOP_CLK_NULL, 1074 CLK_TOP_CLK_NULL, 1075 CLK_TOP_MAINPLL_D12, 1076 CLK_TOP_CLK_NULL, 1077 CLK_TOP_CLK_NULL, 1078 CLK_TOP_CLK_NULL, 1079 CLK_TOP_CLK_NULL, 1080 CLK_TOP_CLK_NULL, 1081 CLK_TOP_CLK_NULL, 1082 CLK_TOP_CLK_NULL, 1083 CLK_TOP_CLK_NULL, 1084 CLK_TOP_CLK_NULL, 1085 CLK_TOP_CLK_NULL, 1086 CLK_TOP_CLK_NULL, 1087 CLK_TOP_CLK_NULL, 1088 CLK_TOP_CLK_NULL, 1089 CLK_TOP_CLK_NULL, 1090 CLK_TOP_CLK_NULL, 1091 CLK_TOP_CLK_NULL, 1092 CLK_TOP_CLK_NULL, 1093 CLK_TOP_CLK_NULL, 1094 CLK_TOP_CLK_NULL, 1095 CLK_TOP_CLK_NULL, 1096 CLK_TOP_CLK_NULL, 1097 CLK_TOP_CLK_NULL, 1098 CLK_TOP_CLK_NULL, 1099 CLK_TOP_CLK_NULL, 1100 CLK_TOP_CLK_NULL, 1101 CLK_TOP_CLK_NULL, 1102 CLK_TOP_CLK_NULL, 1103 CLK_TOP_CLK_NULL, 1104 CLK_TOP_CLK_NULL, 1105 CLK_TOP_CLK_NULL, 1106 CLK_TOP_CLK_NULL, 1107 CLK_TOP_CLK_NULL, 1108 CLK_TOP_CLK_NULL, 1109 CLK_TOP_CLK_NULL, 1110 CLK_TOP_CLK_NULL, 1111 CLK_TOP_CLK_NULL, 1112 CLK_TOP_CLK_NULL, 1113 CLK_TOP_CLK_NULL, 1114 CLK_TOP_CLK_NULL, 1115 CLK_TOP_CLK_NULL, 1116 CLK_TOP_CLK_NULL, 1117 CLK_TOP_CLK_NULL, 1118 CLK_TOP_CLK_NULL, 1119 CLK_TOP_CLK_NULL, 1120 CLK_TOP_CLK_NULL, 1121 CLK_TOP_CLK_NULL, 1122 CLK_TOP_CLK_NULL, 1123 CLK_TOP_CLK_NULL, 1124 CLK_TOP_CLK_NULL, 1125 CLK_TOP_CLK_NULL, 1126 CLK_TOP_CLK_NULL, 1127 CLK_TOP_CLK_NULL, 1128 CLK_TOP_CLK_NULL, 1129 CLK_TOP_CLK_NULL, 1130 CLK_TOP_CLK_NULL, 1131 CLK_TOP_CLK_NULL, 1132 CLK_TOP_CLK_NULL, 1133 CLK_TOP_CLK_NULL, 1134 CLK_TOP_CLK_NULL, 1135 CLK_TOP_CLK_NULL, 1136 CLK_TOP_CLK_NULL, 1137 CLK_TOP_CLK_NULL, 1138 CLK_TOP_CLK_NULL, 1139 CLK_APMIXED_MMPLL 1140}; 1141 1142static const int disp_dpi_ck_parents[] = { 1143 CLK_TOP_CLK_NULL, 1144 CLK_TOP_CLK_NULL, 1145 CLK_TOP_CLK_NULL, 1146 CLK_TOP_CLK_NULL, 1147 CLK_TOP_CLK_NULL, 1148 CLK_TOP_CLK_NULL, 1149 CLK_TOP_CLK_NULL, 1150 CLK_TOP_CLK_NULL, 1151 CLK_TOP_CLK_NULL, 1152 CLK_TOP_CLK26M, 1153 CLK_TOP_TVDPLL_D2, 1154 CLK_TOP_CLK_NULL, 1155 CLK_TOP_TVDPLL_D4, 1156 CLK_TOP_CLK_NULL, 1157 CLK_TOP_CLK_NULL, 1158 CLK_TOP_CLK_NULL, 1159 CLK_TOP_TVDPLL_D8, 1160 CLK_TOP_CLK_NULL, 1161 CLK_TOP_CLK_NULL, 1162 CLK_TOP_CLK_NULL, 1163 CLK_TOP_CLK_NULL, 1164 CLK_TOP_CLK_NULL, 1165 CLK_TOP_CLK_NULL, 1166 CLK_TOP_CLK_NULL, 1167 CLK_TOP_CLK_NULL, 1168 CLK_TOP_CLK_NULL, 1169 CLK_TOP_CLK_NULL, 1170 CLK_TOP_CLK_NULL, 1171 CLK_TOP_CLK_NULL, 1172 CLK_TOP_CLK_NULL, 1173 CLK_TOP_CLK_NULL, 1174 CLK_TOP_CLK_NULL, 1175 CLK_TOP_TVDPLL_D16 1176}; 1177 1178static const struct mtk_composite top_muxes[] = { 1179 /* CLK_MUX_SEL0 */ 1180 MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1), 1181 MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1), 1182 MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1), 1183 MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8), 1184 MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1), 1185 MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1), 1186 MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1), 1187 MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3), 1188 /* CLK_MUX_SEL1 */ 1189 MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3), 1190 MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1), 1191 MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4), 1192 MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3), 1193 /* CLK_MUX_SEL8 */ 1194 MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3), 1195 MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3), 1196 MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1), 1197 MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1), 1198 MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3), 1199 /* CLK_SEL_9 */ 1200 MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1), 1201 MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1), 1202 MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1), 1203 MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1), 1204 /* CLK_MUX_SEL13 */ 1205 MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1), 1206 MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2), 1207 MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1), 1208 MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3), 1209 MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3), 1210 MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1), 1211 /* CLK_MUX_SEL14 */ 1212 MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3), 1213 MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4), 1214 MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4), 1215 MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2), 1216 MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3), 1217 MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3), 1218 MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2), 1219 /* CLK_MUX_SEL15 */ 1220 MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2), 1221 MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2), 1222 MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6), 1223 MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3), 1224 MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3), 1225 /* CLK_MUX_SEL16 */ 1226 MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3), 1227 MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8), 1228 /* CLK_MUX_SEL17 */ 1229 MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3), 1230 MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3), 1231 MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1), 1232 MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2), 1233 MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2), 1234 /* CLK_MUX_SEL19 */ 1235 MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8), 1236 MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8), 1237 /* CLK_MUX_SEL21 */ 1238 MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4), 1239 MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4), 1240 MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4), 1241 /* CLK_MUX_SEL22 */ 1242 MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8), 1243 MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6), 1244 MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8), 1245 MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6), 1246 /* CLK_MUX_SEL23 */ 1247 MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6), 1248 MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8), 1249 MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8), 1250 MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8), 1251}; 1252 1253static const struct mtk_gate_regs top0_cg_regs = { 1254 .set_ofs = 0x50, 1255 .clr_ofs = 0x80, 1256 .sta_ofs = 0x20, 1257}; 1258 1259static const struct mtk_gate_regs top1_cg_regs = { 1260 .set_ofs = 0x54, 1261 .clr_ofs = 0x84, 1262 .sta_ofs = 0x24, 1263}; 1264 1265static const struct mtk_gate_regs top2_cg_regs = { 1266 .set_ofs = 0x6c, 1267 .clr_ofs = 0x9c, 1268 .sta_ofs = 0x3c, 1269}; 1270 1271static const struct mtk_gate_regs top3_cg_regs = { 1272 .set_ofs = 0x44, 1273 .clr_ofs = 0x44, 1274 .sta_ofs = 0x44, 1275}; 1276 1277static const struct mtk_gate_regs top4_cg_regs = { 1278 .set_ofs = 0xa0, 1279 .clr_ofs = 0xb0, 1280 .sta_ofs = 0x70, 1281}; 1282 1283static const struct mtk_gate_regs top5_cg_regs = { 1284 .set_ofs = 0x120, 1285 .clr_ofs = 0x140, 1286 .sta_ofs = 0xe0, 1287}; 1288 1289static const struct mtk_gate_regs top6_cg_regs = { 1290 .set_ofs = 0x128, 1291 .clr_ofs = 0x148, 1292 .sta_ofs = 0xe8, 1293}; 1294 1295static const struct mtk_gate_regs top7_cg_regs = { 1296 .set_ofs = 0x12c, 1297 .clr_ofs = 0x14c, 1298 .sta_ofs = 0xec, 1299}; 1300 1301#define GATE_TOP0(_id, _parent, _shift) { \ 1302 .id = _id, \ 1303 .parent = _parent, \ 1304 .regs = &top0_cg_regs, \ 1305 .shift = _shift, \ 1306 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 1307 } 1308 1309#define GATE_TOP1(_id, _parent, _shift) { \ 1310 .id = _id, \ 1311 .parent = _parent, \ 1312 .regs = &top1_cg_regs, \ 1313 .shift = _shift, \ 1314 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 1315 } 1316 1317#define GATE_TOP2(_id, _parent, _shift) { \ 1318 .id = _id, \ 1319 .parent = _parent, \ 1320 .regs = &top2_cg_regs, \ 1321 .shift = _shift, \ 1322 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 1323 } 1324 1325#define GATE_TOP2_I(_id, _parent, _shift) { \ 1326 .id = _id, \ 1327 .parent = _parent, \ 1328 .regs = &top2_cg_regs, \ 1329 .shift = _shift, \ 1330 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ 1331 } 1332 1333#define GATE_TOP3(_id, _parent, _shift) { \ 1334 .id = _id, \ 1335 .parent = _parent, \ 1336 .regs = &top3_cg_regs, \ 1337 .shift = _shift, \ 1338 .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \ 1339 } 1340 1341#define GATE_TOP4(_id, _parent, _shift) { \ 1342 .id = _id, \ 1343 .parent = _parent, \ 1344 .regs = &top4_cg_regs, \ 1345 .shift = _shift, \ 1346 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 1347 } 1348 1349#define GATE_TOP5(_id, _parent, _shift) { \ 1350 .id = _id, \ 1351 .parent = _parent, \ 1352 .regs = &top5_cg_regs, \ 1353 .shift = _shift, \ 1354 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 1355 } 1356 1357#define GATE_TOP5_I(_id, _parent, _shift) { \ 1358 .id = _id, \ 1359 .parent = _parent, \ 1360 .regs = &top5_cg_regs, \ 1361 .shift = _shift, \ 1362 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ 1363 } 1364 1365#define GATE_TOP6(_id, _parent, _shift) { \ 1366 .id = _id, \ 1367 .parent = _parent, \ 1368 .regs = &top6_cg_regs, \ 1369 .shift = _shift, \ 1370 .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \ 1371 } 1372 1373#define GATE_TOP7(_id, _parent, _shift) { \ 1374 .id = _id, \ 1375 .parent = _parent, \ 1376 .regs = &top7_cg_regs, \ 1377 .shift = _shift, \ 1378 .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \ 1379 } 1380 1381static const struct mtk_gate top_clks[] = { 1382 /* TOP0 */ 1383 GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0), 1384 GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9), 1385 GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10), 1386 GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11), 1387 GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12), 1388 GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16), 1389 GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17), 1390 GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18), 1391 GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19), 1392 /* TOP1 */ 1393 GATE_TOP1(CLK_TOP_THERM, CLK_TOP_AXIBUS_SEL, 1), 1394 GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AXIBUS_SEL, 2), 1395 GATE_TOP1(CLK_TOP_I2C0, CLK_TOP_AHB_INFRA_D2, 3), 1396 GATE_TOP1(CLK_TOP_I2C1, CLK_TOP_AHB_INFRA_D2, 4), 1397 GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_CLK26M, 5), 1398 GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_INFRA_BCLK, 6), 1399 GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_AXIBUS_SEL, 7), 1400 GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_DBG_ATCLK_SEL, 8), 1401 GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AXIBUS_SEL, 9), 1402 GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10), 1403 GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11), 1404 GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_B, 13), 1405 GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14), 1406 GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_CLK26M, 15), 1407 GATE_TOP1(CLK_TOP_I2C2, CLK_TOP_AHB_INFRA_D2, 16), 1408 GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17), 1409 GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18), 1410 GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_SEL, 19), 1411 GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22), 1412 GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI1_SEL, 23), 1413 GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24), 1414 GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27), 1415 GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_PMICSPI_SEL, 28), 1416 GATE_TOP1(CLK_TOP_PMIC_SYSCK, CLK_TOP_CLK26M, 29), 1417 GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30), 1418 GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31), 1419 /* TOP2 */ 1420 GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1), 1421 GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AXIBUS_SEL, 2), 1422 GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AXIBUS_SEL, 4), 1423 GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AXIBUS_SEL, 5), 1424 GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_PWM_SEL, 8), 1425 GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_PWM_SEL, 9), 1426 GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_PWM_SEL, 10), 1427 GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_PWM_SEL, 11), 1428 GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_PWM_SEL, 12), 1429 GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_PWM_SEL, 13), 1430 GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AXIBUS_SEL, 15), 1431 GATE_TOP2(CLK_TOP_CQDMA, CLK_TOP_AXIBUS_SEL, 17), 1432 GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AXIBUS_SEL, 19), 1433 GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AXIBUS_SEL, 20), 1434 GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_SPI1_SEL, 23), 1435 GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AXIBUS_SEL, 24), 1436 GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25), 1437 GATE_TOP2(CLK_TOP_GCPU_B, CLK_TOP_AXIBUS_SEL, 27), 1438 GATE_TOP2_I(CLK_TOP_MSDC0_B, CLK_TOP_MSDC0, 28), 1439 GATE_TOP2_I(CLK_TOP_MSDC1_B, CLK_TOP_MSDC1, 29), 1440 GATE_TOP2_I(CLK_TOP_MSDC2_B, CLK_TOP_MSDC2, 30), 1441 GATE_TOP2(CLK_TOP_USB_B, CLK_TOP_USB_SEL, 31), 1442 /* TOP3 */ 1443 GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0), 1444 GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3), 1445 GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4), 1446 GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8), 1447 /* TOP4 */ 1448 GATE_TOP4(CLK_TOP_SPINOR, CLK_TOP_SPINOR_SEL, 0), 1449 GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1), 1450 GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2), 1451 GATE_TOP4(CLK_TOP_AUD1, CLK_TOP_AUD1_SEL, 8), 1452 GATE_TOP4(CLK_TOP_AUD2, CLK_TOP_AUD2_SEL, 9), 1453 GATE_TOP4(CLK_TOP_I2C, CLK_TOP_I2C_SEL, 12), 1454 GATE_TOP4(CLK_TOP_PWM_INFRA, CLK_TOP_PWM_SEL, 13), 1455 GATE_TOP4(CLK_TOP_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14), 1456 GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15), 1457 GATE_TOP4(CLK_TOP_DBG_AT, CLK_TOP_DBG_ATCLK_SEL, 17), 1458 /* TOP5 */ 1459 GATE_TOP5_I(CLK_TOP_IMGRZ_SYS, CLK_TOP_IMGRZ_SYS_SEL, 0), 1460 GATE_TOP5_I(CLK_TOP_PNG_SYS, CLK_TOP_PNG_SYS_SEL, 1), 1461 GATE_TOP5_I(CLK_TOP_GRAPH_E, CLK_TOP_GRAPH_ECLK_SEL, 2), 1462 GATE_TOP5_I(CLK_TOP_FDBI, CLK_TOP_FDBI_SEL, 3), 1463 GATE_TOP5_I(CLK_TOP_FAUDIO, CLK_TOP_FAUDIO_SEL, 4), 1464 GATE_TOP5_I(CLK_TOP_FAUD_INTBUS, CLK_TOP_FAUD_INTBUS_SEL, 5), 1465 GATE_TOP5_I(CLK_TOP_HAPLL1, CLK_TOP_HAPLL1_SEL, 6), 1466 GATE_TOP5_I(CLK_TOP_HAPLL2, CLK_TOP_HAPLL2_SEL, 7), 1467 GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8), 1468 GATE_TOP5_I(CLK_TOP_FA1SYS, CLK_TOP_FA1SYS_SEL, 9), 1469 GATE_TOP5_I(CLK_TOP_FASM_L, CLK_TOP_FASM_L_SEL, 10), 1470 GATE_TOP5_I(CLK_TOP_FASM_M, CLK_TOP_FASM_M_SEL, 11), 1471 GATE_TOP5_I(CLK_TOP_FASM_H, CLK_TOP_FASM_H_SEL, 12), 1472 GATE_TOP5_I(CLK_TOP_FECC, CLK_TOP_FECC_CK_SEL, 23), 1473 GATE_TOP5_I(CLK_TOP_PE2_MAC, CLK_TOP_PE2_MAC_SEL, 24), 1474 GATE_TOP5_I(CLK_TOP_CMSYS, CLK_TOP_CMSYS_SEL, 25), 1475 GATE_TOP5_I(CLK_TOP_GCPU, CLK_TOP_GCPU_SEL, 26), 1476 GATE_TOP5(CLK_TOP_SPIS, CLK_TOP_SPIS_CK_SEL, 27), 1477 /* TOP6 */ 1478 GATE_TOP6(CLK_TOP_I2C3, CLK_TOP_AHB_INFRA_D2, 0), 1479 GATE_TOP6(CLK_TOP_SPI_SLV_B, CLK_TOP_SPIS_CK_SEL, 1), 1480 GATE_TOP6(CLK_TOP_SPI_SLV_BUS, CLK_TOP_AXIBUS_SEL, 2), 1481 GATE_TOP6(CLK_TOP_PCIE_MAC_BUS, CLK_TOP_AXIBUS_SEL, 3), 1482 GATE_TOP6(CLK_TOP_CMSYS_BUS, CLK_TOP_AXIBUS_SEL, 4), 1483 GATE_TOP6(CLK_TOP_ECC_B, CLK_TOP_AXIBUS_SEL, 5), 1484 GATE_TOP6(CLK_TOP_PCIE_PHY_BUS, CLK_TOP_CLK26M, 6), 1485 GATE_TOP6(CLK_TOP_PCIE_AUX, CLK_TOP_CLK26M, 7), 1486 /* TOP7 */ 1487 GATE_TOP7(CLK_TOP_DISP_DPI, CLK_TOP_DISP_DPI_CK_SEL, 0), 1488}; 1489 1490static const struct mtk_clk_tree mt8518_clk_tree = { 1491 .xtal_rate = 26 * MHZ, 1492 .xtal2_rate = 26 * MHZ, 1493 .fdivs_offs = CLK_TOP_DMPLL, 1494 .muxes_offs = CLK_TOP_UART0_SEL, 1495 .plls = apmixed_plls, 1496 .fclks = top_fixed_clks, 1497 .fdivs = top_fixed_divs, 1498 .muxes = top_muxes, 1499}; 1500 1501static int mt8518_apmixedsys_probe(struct udevice *dev) 1502{ 1503 return mtk_common_clk_init(dev, &mt8518_clk_tree); 1504} 1505 1506static int mt8518_topckgen_probe(struct udevice *dev) 1507{ 1508 return mtk_common_clk_init(dev, &mt8518_clk_tree); 1509} 1510 1511static int mt8518_topckgen_cg_probe(struct udevice *dev) 1512{ 1513 return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks); 1514} 1515 1516static const struct udevice_id mt8518_apmixed_compat[] = { 1517 { .compatible = "mediatek,mt8518-apmixedsys", }, 1518 { } 1519}; 1520 1521static const struct udevice_id mt8518_topckgen_compat[] = { 1522 { .compatible = "mediatek,mt8518-topckgen", }, 1523 { } 1524}; 1525 1526static const struct udevice_id mt8518_topckgen_cg_compat[] = { 1527 { .compatible = "mediatek,mt8518-topckgen-cg", }, 1528 { } 1529}; 1530 1531U_BOOT_DRIVER(mtk_clk_apmixedsys) = { 1532 .name = "mt8518-apmixedsys", 1533 .id = UCLASS_CLK, 1534 .of_match = mt8518_apmixed_compat, 1535 .probe = mt8518_apmixedsys_probe, 1536 .priv_auto = sizeof(struct mtk_clk_priv), 1537 .ops = &mtk_clk_apmixedsys_ops, 1538 .flags = DM_FLAG_PRE_RELOC, 1539}; 1540 1541U_BOOT_DRIVER(mtk_clk_topckgen) = { 1542 .name = "mt8518-topckgen", 1543 .id = UCLASS_CLK, 1544 .of_match = mt8518_topckgen_compat, 1545 .probe = mt8518_topckgen_probe, 1546 .priv_auto = sizeof(struct mtk_clk_priv), 1547 .ops = &mtk_clk_topckgen_ops, 1548 .flags = DM_FLAG_PRE_RELOC, 1549}; 1550 1551U_BOOT_DRIVER(mtk_clk_topckgen_cg) = { 1552 .name = "mt8518-topckgen-cg", 1553 .id = UCLASS_CLK, 1554 .of_match = mt8518_topckgen_cg_compat, 1555 .probe = mt8518_topckgen_cg_probe, 1556 .priv_auto = sizeof(struct mtk_cg_priv), 1557 .ops = &mtk_clk_gate_ops, 1558 .flags = DM_FLAG_PRE_RELOC, 1559}; 1560