1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2022 NXP
4 *
5 * Peng Fan <peng.fan at nxp.com>
6 */
7
8#ifndef __CLOCK_IMX9__
9#define __CLOCK_IMX9__
10
11#include <linux/bitops.h>
12
13#define MHZ(x)	((x) * 1000000UL)
14
15enum enet_freq {
16	ENET_25MHZ = 0,
17	ENET_50MHZ,
18	ENET_125MHZ,
19};
20
21enum ccm_clk_src {
22	OSC_24M_CLK,
23	ARM_PLL,
24	ARM_PLL_CLK,
25	SYS_PLL_PG,
26	SYS_PLL_PFD0_PG,
27	SYS_PLL_PFD0,
28	SYS_PLL_PFD0_DIV2,
29	SYS_PLL_PFD1_PG,
30	SYS_PLL_PFD1,
31	SYS_PLL_PFD1_DIV2,
32	SYS_PLL_PFD2_PG,
33	SYS_PLL_PFD2,
34	SYS_PLL_PFD2_DIV2,
35	AUDIO_PLL,
36	AUDIO_PLL_CLK,
37	DRAM_PLL,
38	DRAM_PLL_CLK,
39	VIDEO_PLL,
40	VIDEO_PLL_CLK,
41	OSCPLL_END,
42	EXT_CLK,
43};
44
45/* Mainly for compatible to imx common code. */
46enum mxc_clock {
47	MXC_ARM_CLK = 0,
48	MXC_IPG_CLK,
49	MXC_FLEXSPI_CLK,
50	MXC_CSPI_CLK,
51	MXC_ESDHC_CLK,
52	MXC_ESDHC2_CLK,
53	MXC_ESDHC3_CLK,
54	MXC_UART_CLK,
55	MXC_I2C_CLK,
56	MXC_FEC_CLK,
57};
58
59struct ccm_obs {
60	u32 direct;
61	u32 reserved[31];
62};
63
64struct ccm_gpr {
65	u32 gpr;
66	u32 gpr_set;
67	u32 gpr_clr;
68	u32 gpr_tog;
69	u32 authen;
70	u32 authen_set;
71	u32 authen_clr;
72	u32 authen_tog;
73};
74
75struct ccm_lpcg_oscpll {
76	u32 direct;
77	u32 lpm_status0;
78	u32 lpm_status1;
79	u32 reserved0;
80	u32 lpm0;
81	u32 lpm1;
82	u32 reserved1;
83	u32 lpm_cur;
84	u32 status0;
85	u32 status1;
86	u32 reserved2[2];
87	u32 authen;
88	u32 reserved3[3];
89};
90
91struct ccm_root {
92	u32 control;
93	u32 control_set;
94	u32 control_clr;
95	u32 control_tog;
96	u32 reserved[4];
97	u32 status0;
98	u32 reserved1[3];
99	u32 authen;
100	u32 reserved2[19];
101};
102
103struct ccm_reg {
104	struct ccm_root clk_roots[95]; /* 0x0 */
105	u32 reserved_0[1312];
106	struct ccm_obs clk_obs[6]; /* 0x4400 */
107	u32 reserved_1[64];
108	struct ccm_gpr clk_shared_gpr[8]; /* 0x4800 */
109	u32 reserved_2[192];
110	struct ccm_gpr clk_private_gpr[8]; /* 0x4C00 */
111	u32 reserved_3[192];
112	struct ccm_lpcg_oscpll clk_oscplls[19]; /* 0x5000 */
113	u32 reserved_4[2768];
114	struct ccm_lpcg_oscpll clk_lpcgs[122]; /* 0x8000 */
115};
116
117struct ana_pll_reg_elem {
118	u32 reg;
119	u32 reg_set;
120	u32 reg_clr;
121	u32 reg_tog;
122};
123
124struct ana_pll_dfs {
125	struct ana_pll_reg_elem dfs_ctrl;
126	struct ana_pll_reg_elem dfs_div;
127};
128
129struct ana_pll_reg {
130	struct ana_pll_reg_elem ctrl;
131	struct ana_pll_reg_elem ana_prg;
132	struct ana_pll_reg_elem test;
133	struct ana_pll_reg_elem ss; /* Spread spectrum */
134	struct ana_pll_reg_elem num; /* numerator */
135	struct ana_pll_reg_elem denom; /* demoninator */
136	struct ana_pll_reg_elem div;
137	struct ana_pll_dfs dfs[4];
138	u32 pll_status;
139	u32 dfs_status;
140	u32 reserved[2];
141};
142
143struct anatop_reg {
144	u32 osc_ctrl;
145	u32 osc_state;
146	u32 reserved_0[510];
147	u32 chip_version;
148	u32 reserved_1[511];
149	struct ana_pll_reg arm_pll;
150	struct ana_pll_reg sys_pll;
151	struct ana_pll_reg audio_pll;
152	struct ana_pll_reg dram_pll;
153	struct ana_pll_reg video_pll;
154};
155
156#define PLL_CTRL_HW_CTRL_SEL BIT(16)
157#define PLL_CTRL_CLKMUX_BYPASS BIT(2)
158#define PLL_CTRL_CLKMUX_EN BIT(1)
159#define PLL_CTRL_POWERUP BIT(0)
160
161#define PLL_STATUS_PLL_LOCK BIT(0)
162#define PLL_DFS_CTRL_ENABLE BIT(31)
163#define PLL_DFS_CTRL_CLKOUT BIT(30)
164#define PLL_DFS_CTRL_CLKOUT_DIV2 BIT(29)
165#define PLL_DFS_CTRL_BYPASS BIT(23)
166
167#define PLL_SS_EN BIT(15)
168
169struct imx_intpll_rate_table {
170	u32 rate; /*khz*/
171	int rdiv;
172	int mfi;
173	int odiv;
174};
175
176struct imx_fracpll_rate_table {
177	u32 rate; /*khz*/
178	int rdiv;
179	int mfi;
180	int odiv;
181	int mfn;
182	int mfd;
183};
184
185#define INT_PLL_RATE(_rate, _r, _m, _o)			\
186	{							\
187		.rate	=	(_rate),			\
188		.rdiv	=	(_r),				\
189		.mfi	=	(_m),				\
190		.odiv	=	(_o),				\
191	}
192
193#define FRAC_PLL_RATE(_rate, _r, _m, _o, _n, _d)			\
194	{							\
195		.rate	=	(_rate),			\
196		.rdiv	=	(_r),				\
197		.mfi	=	(_m),				\
198		.odiv	=	(_o),				\
199		.mfn	=	(_n),				\
200		.mfd	=	(_d),				\
201	}
202
203struct clk_root_map {
204	u32 clk_root_id;
205	u32 mux_type;
206};
207
208struct imx_clk_setting {
209	u32 clk_root;
210	enum ccm_clk_src src;
211	u32 div;
212};
213
214int clock_init(void);
215u32 get_clk_src_rate(enum ccm_clk_src source);
216u32 get_lpuart_clk(void);
217void init_uart_clk(u32 index);
218void init_clk_usdhc(u32 index);
219int enable_i2c_clk(unsigned char enable, u32 i2c_num);
220u32 imx_get_i2cclk(u32 i2c_num);
221u32 mxc_get_clock(enum mxc_clock clk);
222void dram_pll_init(ulong pll_val);
223void dram_enable_bypass(ulong clk_val);
224void dram_disable_bypass(void);
225void set_arm_core_max_clk(void);
226
227int configure_intpll(enum ccm_clk_src pll, u32 freq);
228
229int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable);
230int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable);
231int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable);
232int ccm_clk_src_config_lpm(enum ccm_clk_src oscpll, u32 domain, u32 lpm_val);
233bool ccm_clk_src_is_clk_on(enum ccm_clk_src oscpll);
234int ccm_clk_src_tz_access(enum ccm_clk_src oscpll, bool non_secure, bool user_mode, bool lock_tz);
235int ccm_clk_root_cfg(u32 clk_root_id, enum ccm_clk_src src, u32 div);
236u32 ccm_clk_root_get_rate(u32 clk_root_id);
237int ccm_clk_root_tz_access(u32 clk_root_id, bool non_secure, bool user_mode, bool lock_tz);
238int ccm_lpcg_on(u32 lpcg, bool enable);
239int ccm_lpcg_lpm(u32 lpcg, bool enable);
240int ccm_lpcg_config_lpm(u32 lpcg, u32 domain, u32 lpm_val);
241bool ccm_lpcg_is_clk_on(u32 lpcg);
242int ccm_lpcg_tz_access(u32 lpcg, bool non_secure, bool user_mode, bool lock_tz);
243int ccm_shared_gpr_set(u32 gpr, u32 val);
244int ccm_shared_gpr_get(u32 gpr, u32 *val);
245int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock_tz);
246
247void enable_usboh3_clk(unsigned char enable);
248int set_clk_enet(enum enet_freq type);
249int set_clk_eqos(enum enet_freq type);
250void set_arm_clk(ulong freq);
251#endif
252