/u-boot/drivers/clk/rockchip/ |
H A D | clk_rv1108.c | 34 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 170 return DIV_TO_RATE(pll_rate, div); 191 return DIV_TO_RATE(pll_rate, div); 202 return DIV_TO_RATE(OSC_HZ, div); 227 return DIV_TO_RATE(GPLL_HZ, div); 253 return DIV_TO_RATE(GPLL_HZ, div); 288 return DIV_TO_RATE(GPLL_HZ, div); 317 return DIV_TO_RATE(parent_rate, div); 345 return DIV_TO_RATE(parent_rate, div); 357 return DIV_TO_RATE(parent_rat [all...] |
H A D | clk_rk3308.c | 32 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 205 return DIV_TO_RATE(priv->dpll_hz, div); 269 return DIV_TO_RATE(pll_rate, div); 313 return DIV_TO_RATE(OSC_HZ, div) / 2; 315 return DIV_TO_RATE(priv->vpll0_hz, div) / 2; 369 return DIV_TO_RATE(OSC_HZ, div); 397 return DIV_TO_RATE(OSC_HZ, div); 440 return DIV_TO_RATE(priv->dpll_hz, div); 484 return DIV_TO_RATE(priv->dpll_hz, div); 553 return DIV_TO_RATE(paren [all...] |
H A D | clk_rv1126.c | 31 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 208 return DIV_TO_RATE(priv->gpll_hz, div); 261 return DIV_TO_RATE(priv->gpll_hz, div); 322 return DIV_TO_RATE(priv->gpll_hz, div); 350 return DIV_TO_RATE(priv->gpll_hz, div); 574 return DIV_TO_RATE(priv->gpll_hz, div); 635 return DIV_TO_RATE(parent, div); 705 return DIV_TO_RATE(parent, div); 745 return DIV_TO_RATE(priv->gpll_hz, div); 788 return DIV_TO_RATE(pri [all...] |
H A D | clk_rk3588.c | 23 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 281 return DIV_TO_RATE(prate, div); 292 return DIV_TO_RATE(prate, div); 650 return DIV_TO_RATE(prate, div); 661 return DIV_TO_RATE(prate, div); 743 return DIV_TO_RATE(prate, div); 755 return DIV_TO_RATE(prate, div); 765 return DIV_TO_RATE(prate, div); 777 return DIV_TO_RATE(prate, div); 787 return DIV_TO_RATE(prat [all...] |
H A D | clk_rk3328.c | 34 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 365 return DIV_TO_RATE(GPLL_HZ, div); 409 return DIV_TO_RATE(GPLL_HZ, src_clk_div); 444 return DIV_TO_RATE(pll_rate, div); 471 return DIV_TO_RATE(OSC_HZ, div) / 2; 473 return DIV_TO_RATE(GPLL_HZ, div) / 2; 522 return DIV_TO_RATE(GPLL_HZ, div); 534 return DIV_TO_RATE(GPLL_HZ, div); 545 return DIV_TO_RATE(OSC_HZ, div); 569 return DIV_TO_RATE(OSC_H [all...] |
H A D | clk_rk3128.c | 30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 307 return DIV_TO_RATE(src_rate, div); 367 return DIV_TO_RATE(PERI_ACLK_HZ, div); 391 return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div); 402 return DIV_TO_RATE(OSC_HZ, div); 481 return DIV_TO_RATE(parent, div);
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H A D | clk_px30.c | 54 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 315 return DIV_TO_RATE(priv->gpll_hz, div); 487 return DIV_TO_RATE(priv->gpll_hz, div); 535 return DIV_TO_RATE(OSC_HZ, div) / 2; 537 return DIV_TO_RATE(priv->gpll_hz, div) / 2; 591 return DIV_TO_RATE(priv->gpll_hz, div); 628 return DIV_TO_RATE(priv->gpll_hz, div); 670 return DIV_TO_RATE(OSC_HZ, div); 696 return DIV_TO_RATE(OSC_HZ, div); 733 return DIV_TO_RATE(pri [all...] |
H A D | clk_rk3368.c | 46 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 197 rate = DIV_TO_RATE(pll_rate, div); 350 return DIV_TO_RATE(pll_rate, div); 402 return DIV_TO_RATE(GPLL_HZ, div); 440 return DIV_TO_RATE(OSC_HZ, div);
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H A D | clk_rk3399.c | 50 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 553 return DIV_TO_RATE(GPLL_HZ, div); 652 return DIV_TO_RATE(GPLL_HZ, div); 754 return DIV_TO_RATE(OSC_HZ, div); 756 return DIV_TO_RATE(GPLL_HZ, div); 901 return DIV_TO_RATE(GPLL_HZ, div); 912 return DIV_TO_RATE(OSC_HZ, div); 1564 return DIV_TO_RATE(PPLL_HZ, div); 1593 return DIV_TO_RATE(PPLL_HZ, src_clk_div); 1604 return DIV_TO_RATE(PPLL_H [all...] |
H A D | clk_rk3066.c | 72 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 279 return DIV_TO_RATE(gclk_rate, div) / 2; 337 return DIV_TO_RATE(gclk_rate, div); 382 return DIV_TO_RATE(PERI_PCLK_HZ, div);
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H A D | clk_rk3568.c | 39 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 240 return DIV_TO_RATE(priv->ppll_hz, div); 284 return DIV_TO_RATE(parent, div); 330 return DIV_TO_RATE(parent, div); 649 return DIV_TO_RATE(priv->cpll_hz, div); 1223 return DIV_TO_RATE(prate, div); 1228 return DIV_TO_RATE(prate, div); 1729 return DIV_TO_RATE(parent, div); 1787 return DIV_TO_RATE(parent, div); 2066 p_rate = DIV_TO_RATE(pri [all...] |
H A D | clk_rk3288.c | 137 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 336 return DIV_TO_RATE(pll_rate, div); 607 return DIV_TO_RATE(src_rate, div); 687 return DIV_TO_RATE(gclk_rate, div); 732 return DIV_TO_RATE(OSC_HZ, div);
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H A D | clk_rk322x.c | 31 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 242 return DIV_TO_RATE(src_rate, div) / 2; 274 return DIV_TO_RATE(pll_rate, div);
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H A D | clk_rk3188.c | 75 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 288 return DIV_TO_RATE(gclk_rate, div) / 2; 346 return DIV_TO_RATE(gclk_rate, div);
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H A D | clk_rk3036.c | 33 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) macro 239 return DIV_TO_RATE(src_rate, div) / 2;
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