/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt8365.c | 425 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7), 484 .muxes_offs = CLK_TOP_AXI_SEL, 617 GATE_IFR2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8), 618 GATE_IFR2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9), 619 GATE_IFR2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10), 620 GATE_IFR2(CLK_IFR_PWM_HCLK, CLK_TOP_AXI_SEL, 15), 632 GATE_IFR2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28), 633 GATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31), 638 GATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4), 640 GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, [all...] |
H A D | clk-mt7622.c | 312 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), 384 GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0), 385 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2), 423 GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1), 432 GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12), 435 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17), 436 GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18), 437 GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19), 438 GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20), 439 GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 2 [all...] |
H A D | clk-mt7623.c | 183 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4), 509 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), 598 GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0), 600 GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2), 607 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13), 610 GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16), 612 GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19), 614 GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23), 615 GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24), 649 GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, [all...] |
H A D | clk-mt8512.c | 450 MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents, 725 GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8), 727 GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6), 728 GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8), 729 GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9), 730 GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10), 731 GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15), 743 GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28), 744 GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31), 748 GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, [all...] |
H A D | clk-mt7629.c | 134 FACTOR1(CLK_TOP_HD_FAXI, CLK_TOP_AXI_SEL, 1, 1), 135 FACTOR1(CLK_TOP_FAXI, CLK_TOP_AXI_SEL, 1, 1), 144 FACTOR1(CLK_TOP_TO_USB3_MCU, CLK_TOP_AXI_SEL, 1, 1), 146 FACTOR1(CLK_TOP_FROM_TOP_AHB, CLK_TOP_AXI_SEL, 1, 1), 365 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7), 570 .muxes_offs = CLK_TOP_AXI_SEL,
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/u-boot/dts/upstream/include/dt-bindings/clock/ |
H A D | mt8135-clk.h | 73 #define CLK_TOP_AXI_SEL 62 macro
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H A D | mt7629-clk.h | 83 #define CLK_TOP_AXI_SEL 73 macro
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/u-boot/arch/nios2/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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H A D | mt8512-clk.h | 69 #define CLK_TOP_AXI_SEL 58 macro
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/u-boot/arch/sandbox/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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H A D | mt8512-clk.h | 69 #define CLK_TOP_AXI_SEL 58 macro
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/u-boot/arch/arm/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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H A D | mt8512-clk.h | 69 #define CLK_TOP_AXI_SEL 58 macro
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/u-boot/arch/microblaze/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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H A D | mt8512-clk.h | 69 #define CLK_TOP_AXI_SEL 58 macro
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H A D | mt7622-clk.h | 69 #define CLK_TOP_AXI_SEL 56 macro
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/u-boot/arch/mips/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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H A D | mt8512-clk.h | 69 #define CLK_TOP_AXI_SEL 58 macro
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H A D | mt7622-clk.h | 69 #define CLK_TOP_AXI_SEL 56 macro
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/u-boot/arch/x86/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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H A D | mt8512-clk.h | 69 #define CLK_TOP_AXI_SEL 58 macro
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/u-boot/arch/xtensa/dts/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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H A D | mt8512-clk.h | 69 #define CLK_TOP_AXI_SEL 58 macro
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/u-boot/include/dt-bindings/clock/ |
H A D | mt7629-clk.h | 87 #define CLK_TOP_AXI_SEL 73 macro
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H A D | mt8512-clk.h | 69 #define CLK_TOP_AXI_SEL 58 macro
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