Lines Matching refs:CLK_TOP_AXI_SEL
183 FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
509 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
598 GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
600 GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
607 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
610 GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
612 GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
614 GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
615 GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
649 GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
657 GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
660 GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
666 GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
667 GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
668 GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
669 GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
670 GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
671 GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
672 GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
673 GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
674 GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
679 GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
681 GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
682 GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1),
683 GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
687 GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6),
737 .muxes_offs = CLK_TOP_AXI_SEL,