Lines Matching refs:CLK_TOP_AXI_SEL
312 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
384 GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
385 GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
423 GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
432 GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
435 GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
436 GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
437 GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
438 GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
439 GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
440 GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
441 GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
442 GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
447 GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
448 GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31),
473 GATE_PCIE(CLK_PCIE_P1_AHB_EN, CLK_TOP_AXI_SEL, 14),
479 GATE_PCIE(CLK_PCIE_P0_AHB_EN, CLK_TOP_AXI_SEL, 20),
483 GATE_PCIE(CLK_SATA_AHB_EN, CLK_TOP_AXI_SEL, 26),
549 GATE_SSUSB(CLK_SSUSB_MCU_EN, CLK_TOP_AXI_SEL, 7),
557 .muxes_offs = CLK_TOP_AXI_SEL,