Lines Matching refs:CLK_TOP_AXI_SEL
425 MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x040, 0, 2, 7),
484 .muxes_offs = CLK_TOP_AXI_SEL,
617 GATE_IFR2(CLK_IFR_ICUSB, CLK_TOP_AXI_SEL, 8),
618 GATE_IFR2(CLK_IFR_GCE, CLK_TOP_AXI_SEL, 9),
619 GATE_IFR2(CLK_IFR_THERM, CLK_TOP_AXI_SEL, 10),
620 GATE_IFR2(CLK_IFR_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
632 GATE_IFR2(CLK_IFR_CQ_DMA_FPC, CLK_TOP_AXI_SEL, 28),
633 GATE_IFR2(CLK_IFR_BTIF, CLK_TOP_AXI_SEL, 31),
638 GATE_IFR3(CLK_IFR_MSDC1_HCLK, CLK_TOP_AXI_SEL, 4),
640 GATE_IFR3(CLK_IFR_GCPU, CLK_TOP_AXI_SEL, 8),
641 GATE_IFR3(CLK_IFR_TRNG, CLK_TOP_AXI_SEL, 9),
644 GATE_IFR3(CLK_IFR_AP_DMA, CLK_TOP_AXI_SEL, 18),
645 GATE_IFR3(CLK_IFR_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
646 GATE_IFR3(CLK_IFR_AUDIO, CLK_TOP_AXI_SEL, 25),
651 GATE_IFR4(CLK_IFR_CQ_DMA, CLK_TOP_AXI_SEL, 27),
670 GATE_IFR5(CLK_IFR_NIC_AXI, CLK_TOP_AXI_SEL, 28),
671 GATE_IFR5(CLK_IFR_NIC_SLV_AXI, CLK_TOP_AXI_SEL, 29),
672 GATE_IFR5(CLK_IFR_APU_AXI, CLK_TOP_AXI_SEL, 30),
677 GATE_IFR6(CLK_IFR_NFI_BK, CLK_TOP_AXI_SEL, 3),
678 GATE_IFR6(CLK_IFR_MSDC2_AP_BK, CLK_TOP_AXI_SEL, 4),
679 GATE_IFR6(CLK_IFR_MSDC2_MD_BK, CLK_TOP_AXI_SEL, 5),
680 GATE_IFR6(CLK_IFR_MSDC2_BK, CLK_TOP_AXI_SEL, 6),
681 GATE_IFR6(CLK_IFR_SUSB_133_BK, CLK_TOP_AXI_SEL, 7),
682 GATE_IFR6(CLK_IFR_SUSB_66_BK, CLK_TOP_AXI_SEL, 8),